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2013-11-28Remove "high 16" register class macros for xmm/ymm/zmmH. Peter Anvin1-9/+3
The "high 16" register class macros were actually incorrect, as they simply aliased the corresponding whole set class. In oder to keep someone from getting confused and making mistakes, remove them. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-27opflags: Separate vector registers into low-16 and high-16Jin Kyu Song1-4/+23
Since only EVEX supports all 32 vector registers encoding for now, VEX/REX encoded instructions should not take high-16 registers as operands. This filtering had been done using instruction flag so far, but using the opflags makes more sense. [XYZ]MMREG operands used for non-EVEX instructions are automatically converted to [XYZ]MM_L16 in insns.pl Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Add MPX instructionsJin Kyu Song1-1/+4
Added MPX instructions and corresponding parser and encoder. ICC style mib - base + disp and index are separate - is supported. E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index As a supplement to NASM style mib - split EA - parser, omitted base+disp is now treated as 0 displacement. E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-08-29AVX-512: Add OPMASK instructionsJin Kyu Song1-1/+3
Added opmask instructions (kandw and etc). Defined KREG and RM_K aliasing RM_OPMASK and OPMASKREG respectively to make insns.dat look neat. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-16AVX-512: Add EVEX encoding and new instructionsJin Kyu Song1-3/+3
EVEX encoding support includes 32 vector regs (XMM/YMM/ZMM), opmask, broadcasting, embedded rounding mode, suppress all exceptions, compressed displacement. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-06AVX-512: Add support for parsing bracesJin Kyu Song1-6/+15
AVX-512 introduced new syntax using braces for decorators. Opmask, broadcat, rounding control use this new syntax. http://software.intel.com/sites/default/files/319433-015.pdf Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-07-19BR 3392260: Handle instructions only separated by vector SIB sizeH. Peter Anvin1-0/+2
There are two instructions (VGATHERQPS, VPGATHERQD) where the only separation between two forms is the vector length given to the vector SIB. This means the *matcher* has to be able to distinguish instructions by vector SIB length and the matcher only operates on the operands and the instruction flags, not on the bytecode. Export the vector index-ness into the operand flags and add to the matcher. This resolves BR 3392260. Reported-by: Agner <agner@anger.org> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-03-04Drop SAME_AS flag from instruction matcherBen Rudiak-Gould1-3/+0
It was there to support the SSE5 DREX encoding, which as far as I know is dead forever. Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-03insns: Remove pushseg/popseg internal bytecodesBen Rudiak-Gould1-4/+10
This patch is getting rid of the following bytecodes 'pushseg','popseg','pushseg2','popseg2' and simplifies overall code. [gorcunov@: a few style fixes] Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-01Remove +sBen Rudiak-Gould1-11/+6
It doesn't seem worth >200 lines of C and Perl to save ~50 lines in insns.dat. In order to make this work I had to rename sbyte16/sbyte32 so that they can take an ordinary size suffix (their size suffix was formerly treated specially). This fixes one disassembly bug: 48C7C000000080 disassembles to mov rax,0x80000000, which reassembles to B800000080, which loads a different value. Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Acked-by: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2012-09-16opflags: Rework opflags bits with OP_ macrosCyrill Gorcunov1-163/+163
In this path the opflags bits are completely reworked in a sake of simplier extension. Inparticular for Knights Corener instructions we will need new registers and new sizes. What's done - all bits are grouped in sequences, and start using OP_ macros, thus if one need to extend some field -- just tune up @shift and @bits where needed - the #define we use in code are OR'ed in symbols, this should be a way more convenient to deal with instead of pure hex numbers. The tests are passed but more eyes needed to review this rather big and intrusive patch. The reason why it's done in one single path -- for revertability in one command. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2012-09-16opflags: Introduce opflags generating macrosCyrill Gorcunov1-0/+4
This patch introduces two macros - OP_GENMASK, to generate masks in opflags - OP_GENBIT, to generate bit at specified position we will use them with extended 64 bits opflags. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2012-09-16opflags: Drop never used REG_RIP/REG_EIPCyrill Gorcunov1-3/+0
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2012-09-10opflags: Extend opflags_t to 64 bitsCyrill Gorcunov1-84/+84
Soon we will need to encode 512 bits values thus there is no space left in our opflags_t which is 32 bitfield. Extend it to 64 bits width. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2011-08-28Add IS_SREG and IS_FSGS helpersCyrill Gorcunov1-0/+3
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2010-08-24Optimize mov r64,immH. Peter Anvin1-7/+8
Handle immediate-size optimization for "mov r64,imm" -- reduce it to "mov r32,imm32" or "mov r64,imm32" as appropriate. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2009-10-13opflags: more int32_t -> opflags_t conversionsH. Peter Anvin1-0/+239
Hopefully this should catch all of them... but please keep an eye out for any other uses of int32_t for the operand flags. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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