Age | Commit message (Collapse) | Author | Files | Lines |
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Implement Centaur's XCRYPT instruction (RFE 825529)
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0FC2 is not really an instruction prefix; it's the opcode for
CMPPS/CMPSS, which takes a control immediate which Intel chose to have
opcode aliases for. However, we can't dispatch on a tail byte, so
it's useless.
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Modify the disassembler so that we can have separate instruction
tables for prefixed instructions. As it was, all instructions which
started with 0F were linearly searched, and that is by now more than
half the instruction set.
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Support for the SSE5 instruction format in the disassembler.
Also adds some comments to insnsd.c for easier debugging.
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This checkin completes what is required to actually generate SSE5
instructions. No support in the disassembler yet.
This checkin covers:
- Support for actually generating DREX prefixes.
- Support for matching operand "operand X must match Y"
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For SSE5, we will need to support four arguments per instruction.
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Support r/m operands for non-integer operands types, i.e. mmx or xmm
operands. This allows mmx and xmm operands to be written more
compactly, speeding up the assembler.
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We have a lot of enumerations; by declaring fields as such, we make it
easier when debugging, since the debugger can display the enumerations
in cleartext. However, make sure exceptional values (like -1) are
included in the enumeration, since the compiler otherwise may not
include it in the valid range of the enumeration.
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When we're dealing with a field which is guaranteed to have an enum type,
then declare it as such so it shows up in debuggers.
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Make the big instruction arrays "const", so they end up in readonly
storage. While we're at it, move their prototypes into insns.h.
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Use an actual named enum for the opcode, that way it shows up in
cleartext while debugging.
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