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2013-11-28Add {vex3} and {vex2} prefixes by analogy with {evex}H. Peter Anvin1-1/+5
Allow specifying {vex3} or {vex2} (the latter is currently always redundant, unless we end up with instructions at some point can be specified with legacy prefixes or VEX) to select a specific encoding of VEX-encoded instructions. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-11-27iflags: Add IF_EVEX for checking {evex} availabilityJin Kyu Song1-3/+1
For checking the availability of {evex} prefix, AVX512 iflag has been used. But this is a flag for an instruction set not for an encoding scheme. And there are some AVX512 instructions encoded with VEX prefix. So a new instruction flag (IF_EVEX) is added for the instructions which are actually encoded with EVEX prefix. This flag is automatically added by insns.pl, so no need to add manually in insns.dat. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-27opflags: Separate vector registers into low-16 and high-16Jin Kyu Song1-0/+5
Since only EVEX supports all 32 vector registers encoding for now, VEX/REX encoded instructions should not take high-16 registers as operands. This filtering had been done using instruction flag so far, but using the opflags makes more sense. [XYZ]MMREG operands used for non-EVEX instructions are automatically converted to [XYZ]MM_L16 in insns.pl Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-24iflag: Fix dependencies, factor out static components of iflag.hH. Peter Anvin1-3/+7
Multi-dependencies don't work as expected, especially not across Make versions, this is why we don't use them and read the instructions list multiple times. iflag.h has a lot of static content, so factor out the static content. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-24insns: Restore back MMX,FPU flagsCyrill Gorcunov1-15/+0
In commit 9bb987d8e0330429afba42015b1fc7c7ca0d1b16 we had to drop some flags due to flags type used in nasm code. Since now flags internal structure is reworked, we can restore them back. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-11-24iflag: Start using new instruction flags engineCyrill Gorcunov1-6/+19
Here we start using instruction flags generator. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-11-20MPX: Move BND prefix indication from bytecode to iflagsJin Kyu Song1-1/+0
As BND prefix validity check conflicts with jcc8 prefix, IF_BND is added for the instruction templates which can have bnd prefix for preserving the content of bound register. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Add BND prefix for branch instructionsJin Kyu Song1-0/+1
BND prefix is used for adding bounds checking protection across flow control changes such as call, ret, jmp and jcc calls. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Add MPX instructionsJin Kyu Song1-0/+3
Added MPX instructions and corresponding parser and encoder. ICC style mib - base + disp and index are separate - is supported. E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index As a supplement to NASM style mib - split EA - parser, omitted base+disp is now treated as 0 displacement. E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-10-07iflags: Eliminate perl smart match operatorJin Kyu Song1-1/+1
As smart match operator reuiqres perl version 5.10.1 or later, it is replaced with grep function. This part of code is going to be completely removed once iflags renovataion is done. This commit is a quick fix for a build error. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-08-28AVX-512: Change the data type for instruction flagsJin Kyu Song1-0/+15
Increased the size of data type for instruction flags from 32bits to 64bits. And a new type (iflags_t) is defined for better maintainability. Bigger data type is needed because more instruction set types are coming but there were not enough space for them. Since they are not bit masks, only one instruction set is allowed for each instruction. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-16AVX-512: Add EVEX encoding and new instructionsJin Kyu Song1-13/+127
EVEX encoding support includes 32 vector regs (XMM/YMM/ZMM), opmask, broadcasting, embedded rounding mode, suppress all exceptions, compressed displacement. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-10Make F2 and F3 SSE prefixes override 66Ben Rudiak-Gould1-2/+2
According to XED and experimentation, the 66 is ignored. Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-04Drop SAME_AS flag from instruction matcherBen Rudiak-Gould1-17/+13
It was there to support the SSE5 DREX encoding, which as far as I know is dead forever. Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-03insns: Remove pushseg/popseg internal bytecodesBen Rudiak-Gould1-12/+0
This patch is getting rid of the following bytecodes 'pushseg','popseg','pushseg2','popseg2' and simplifies overall code. [gorcunov@: a few style fixes] Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-02insns.pl: Various style polyshingCyrill Gorcunov1-75/+77
- convert tabs to spaces - align octal opcodes No func changes. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-01Remove +sBen Rudiak-Gould1-33/+5
It doesn't seem worth >200 lines of C and Perl to save ~50 lines in insns.dat. In order to make this work I had to rename sbyte16/sbyte32 so that they can take an ordinary size suffix (their size suffix was formerly treated specially). This fixes one disassembly bug: 48C7C000000080 disassembles to mov rax,0x80000000, which reassembles to B800000080, which loads a different value. Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Acked-by: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-02-20Add np and similar prefixes to instructions that should have themBen Rudiak-Gould1-0/+2
This adds "np" to a bunch of SSE-style instructions that should have it, "norep" (which was implemented but unused) on quasi-SSE instructions that use F2 and F3 as instruction extensions but 66 for operand size, "nof3" (newly implemented) on a few instructions, "norexw" on some instructions that have only 32-bit and 64-bit versions, and one NOLONG. It also removes some incorrect "np"s, changes some "f3"s to "f3i"s, and fixes the decoding of the XCHG/NOP/PAUSE mess: F390 is always PAUSE even when rex.b=1 (at least according to XED). Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2012-02-25HLE: Move byte codes back to \271-\273H. Peter Anvin1-3/+3
Since we are back to three bytecodes, move them back to the \271-\273 slot to free up the \264 complete quad. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-25HLE: Change NOHLE to be an instruction flagH. Peter Anvin1-1/+0
The way our matching system works we have to make NOHLE an instruction flag rather than an byte code; by the time we run the byte code interpreter we have already picked an instruction pattern once and for all. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-25Remove all remaining explicit bytecodes from insns.datH. Peter Anvin1-12/+31
Get rid of the last vestiges of the explicit byte codes in insns.dat. The only files that now depend on actual byte code numbers are insns.pl, assemble.c and disasm.c. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-25Move HLE byte codes to \264..\267H. Peter Anvin1-4/+4
Move the HLE byte codes to \264..\267 so as not to break up an unused group of 8 (\240..\247). Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-25Add a "nohle" byte code to skip an instruction patternH. Peter Anvin1-3/+4
The a2/a3 mem_offs MOV opcodes are invalid with XRELEASE; those instructions instead have to use a modrm form. Therefore give a way to annotate those instruction patters so the pattern matcher will move on to the next pattern, rather than selecting them and then issue a warning. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-24insns.pl: Bundle all "plain bytecodes" into a hashH. Peter Anvin1-40/+33
Instead of a long string of ifs, put all the plain opcodes which just turn into single bytecodes with no other effect into a hash. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-24HLE: Implement the basic mechanism for XACQUIRE/XRELEASEH. Peter Anvin1-0/+6
This implements the mechanism for XACQUIRE/XRELEASE. It does not include the necessary annotations in insns.dat. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-10insns: create a symbolic "wait" token for the \341 byte codeH. Peter Anvin1-0/+2
Create a symbolic name "wait" for the \341 byte code, so we don't have to open-code it. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-09insns: replace open-coded \322 opcode with odf (operand default)H. Peter Anvin1-0/+2
Create a mnemonic for the open-coded opcode \322. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2011-07-20Implement insns.dat in human readable formAnonymous1-74/+58
I converted almost all instructions in insns.dat (version 7a6f97869840fc0b1b8677bd77c74754c5f024aa) to the more readable format that insns.pl has supported for years. I also made some changes to insns.pl. You can verify that the new insns.dat and insns.pl produce byte-identical output to the old insns.dat and insns.pl, so I think that this change is safe to check in, even though it is a large change to insns.dat. The changes to insns.pl are: * fixed a bug: ib,u was not recognized * added support for a second immediate argument called "j" for instructions like ENTER imm,imm * added a "+r" syntax for \10..\13 [gorcunov: insns files remains the same, great job anonymous!] Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2011-07-07Use a normal quad-case for valueless /is4H. Peter Anvin1-3/+4
When we don't have an immediate for the i-field in /is4, then use a normal quad-bytecode encoding for it to save some small amount of space and re-use existing machinery. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-07-07Remove support for DREX encodingH. Peter Anvin1-14/+0
The DREX encoding never hit production silicon, and has been replaced by VEX/XOP encoding, so remove support for it. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-06-22Add support for VSIB instructionsH. Peter Anvin1-0/+5
Add support for VSIB instructions, which use vector registers as the index registers in an EA. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2010-11-23insns.pl: Fix up merge conflict for sureCyrill Gorcunov1-1/+1
Now it should be fixed in real (one code snipped escaped me during merge conflict resolving). Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2010-11-23insns.pl: Clear tabs/space messCyrill Gorcunov1-520/+520
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2010-08-19insns.pl: make insnsd.c a bit easier to readH. Peter Anvin1-11/+8
Formatting changes (no object code difference) to insnsd.c for readability. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2010-08-19ndisasm: handle VEX.LIGH. Peter Anvin1-6/+6
A lot of instructions ignore the L bit in the VEX prefix, just like a lot of instructions ignore the W bit, so don't use them in the sub-table select. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2010-08-16assemble: handle vex.ligH. Peter Anvin1-2/+4
AVX version 7 introduces the concept of .lig, meaning VEX.L is ignored. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2010-08-16vex: change .wx to .wig to match the latest AVX specH. Peter Anvin1-1/+1
Change the .wx (ignore the W field) to .wig, to match the latest version of the AVX specification. This is not a functional change, but just makes instruction patterns a little easier to write. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2009-08-08insns.pl: remove redundant empty line in enum opcodeCyrill Gorcunov1-1/+1
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-07-26insns.pl: smarter handling of operand flagsH. Peter Anvin1-12/+31
Handle operand flags like "xmmrm128" correctly. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-07-06NASM: relicense under the 2-clause BSD licenseH. Peter Anvin1-12/+0
*To the best of my knowledge*, we now have authorization from everyone who has significantly contributed to NASM in the past. As such, change the license to the 2-clause BSD license. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-06-28Add copyright verbiage to Perl scripts; update LICENSEH. Peter Anvin1-5/+47
This adds copyright verbiage to the Perl scripts. Scripts that are known to be clean w.r.t. the 2-clause BSD license are given that license; unclear ones are given the "LGPL for now". Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-06-25insns.pl: remove stray whitespaceH. Peter Anvin1-1/+1
Clean up whitespace in insns.pl. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-06-25insns.pl: add "nohi" code for REX_NHH. Peter Anvin1-0/+2
Add a "nohi" code flag for the \325 byte code, which sets the REX_NH flag. That is, REX_P not required to support high registers, high registers are not supported and spl/bpl/sil/dil enabled even in non-64-bit mode. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-06-25insns.pl: fix indentationH. Peter Anvin1-141/+141
Canonicalize indentation of some blocks. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-06-24insns.pl: allow relaxed forms to be created without duplicationH. Peter Anvin1-32/+77
Allow a * to be put on an operand, indicating that it is optional and should be replaced with the immediately preceding operand if it is omitted. This allows official and relaxed forms of nondestructive instructions to be written on one line. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-05-15insns.pl - add handling of pp VEX/XOP fieldsCyrill Gorcunov1-3/+5
We already have such kind of aliases for L field (via l0 and l1). Via p0,p1,p2 it's become easier to follow AMD docs while encoding VEX/XOP commands. Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-05-03Use lower case for VEX and XOP in instructions tableH. Peter Anvin1-3/+3
Use lower case for VEX and XOP ("vex", "xop") to avoid visual confusion (and in the future potential real confusion) with upper-case hexadecimal numbers. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-05-03Infrastructure support for AMD's new XOP prefixH. Peter Anvin1-23/+38
Handle AMD's XOP prefixes; they use basically the same encoding as VEX prefixes, so treat them simply as a variant of VEX. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-02-18insns.pl: handle the new VEX.DDS flag per AVX spec version 5H. Peter Anvin1-1/+1
The AVX spec version 5 introduces the new VEX.DDS flag; support it.
2008-10-23Add extension bytecodes to support operands 4+H. Peter Anvin1-29/+55
The bytecode format assumes max 4 operands pretty strictly, but we already have one instruction with 5 operands, and it's likely to get more. Support them via extension prefixes (similar to REX prefixes). For bytecodes which use argument bytes we encode the number directly, however. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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