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AgeCommit message (Expand)AuthorFilesLines
2013-11-24iflag: Start using new instruction flags engineCyrill Gorcunov1-116/+2
2013-11-20PREFETCHWT1: Add a new instruction flagJin Kyu Song1-0/+1
2013-11-20MPX: Move BND prefix indication from bytecode to iflagsJin Kyu Song1-0/+1
2013-11-20iflags: Use UINT64_C() for 64bit valuesJin Kyu Song1-79/+79
2013-11-20SHA: Add SHA instructionsJin Kyu Song1-0/+1
2013-11-20MPX: Add MPX instructionsJin Kyu Song1-0/+1
2013-11-20disasm: add support for emitting split EA formatH. Peter Anvin1-0/+1
2013-09-14AVX-512: Added AVX-512PF instructionsJin Kyu Song1-0/+1
2013-09-14AVX-512: Add AVX-512ER instructionsJin Kyu Song1-2/+3
2013-09-14AVX-512: Add AVX-512CD instructionsJin Kyu Song1-0/+1
2013-08-29AVX-512: Add IF_SPMASK and fix IF_PFMASKJin Kyu Song1-1/+2
2013-08-28AVX-512: Change the data type for instruction flagsJin Kyu Song1-25/+28
2013-08-16AVX-512: Add EVEX encoding and new instructionsJin Kyu Song1-3/+7
2013-05-10Add IF_TBM flagCyrill Gorcunov1-0/+1
2012-02-25HLE: Change NOHLE to be an instruction flagH. Peter Anvin1-22/+24
2012-02-25Add support for warning on invalid LOCK prefixesH. Peter Anvin1-0/+1
2012-02-09insns: Add AVX2 transactional synchronization extensionsCyrill Gorcunov1-0/+2
2011-07-17Some cleanup on insns.hCyrill Gorcunov1-75/+78
2011-07-08A few more AVX2 spec instructionsH. Peter Anvin1-0/+1
2011-07-07insns.h: Add BMI1 and BMI2 flags for further usageJasper Neuman1-0/+2
2011-06-25Add IF_AVX2 flagCyrill Gorcunov1-0/+1
2010-08-24assemble: add an OPT instruction flags for optimizing assembly onlyH. Peter Anvin1-1/+2
2010-08-19ndisasm: handle VEX.LIGH. Peter Anvin1-1/+1
2009-07-25Enable fuzzy matching of operand sizesH. Peter Anvin1-11/+14
2009-05-03Use lower case for VEX and XOP in instructions tableH. Peter Anvin1-1/+1
2009-05-03Infrastructure support for AMD's new XOP prefixH. Peter Anvin1-1/+1
2009-02-21FMA instructions won't be in Sandy BridgeH. Peter Anvin1-0/+1
2008-05-23AVX FMA: Instruction table for the AVX FMA instructionsH. Peter Anvin1-1/+2
2008-05-21Disassembler: select table based on VEX prefixesH. Peter Anvin1-0/+1
2008-05-20Add DY, YWORD, and the SY instruction flagH. Peter Anvin1-1/+2
2008-05-13Make insnsb.c an actual compilation unitH. Peter Anvin1-0/+3
2008-05-12Generate a byte array instead of using strings for the byte codesH. Peter Anvin1-1/+1
2008-05-06Actually spell "Sandy Bridge" correctlyH. Peter Anvin1-1/+1
2008-05-06Sandy Bridge, not Sandy Banks; add WestmereH. Peter Anvin1-1/+2
2008-05-04First cut at AVX machinery.H. Peter Anvin1-0/+2
2008-04-04Correctly identify SBYTE in the optimizerH. Peter Anvin1-1/+3
2007-12-29regularized spelling of license to match name of LICENSE fileBeroset1-1/+1
2007-09-24Support __float*__ for floating-point numbers in expressionsH. Peter Anvin1-7/+1
2007-09-22Add the AMD SSE4a and LZCNT instructionsH. Peter Anvin1-2/+3
2007-09-18Support generating NaNs and infinitiesH. Peter Anvin1-2/+2
2007-09-18Speed up the disassembler by allowing prefixed instruction tablesH. Peter Anvin1-1/+10
2007-09-18Implement "oword" (128 bits) as a first-class sizeH. Peter Anvin1-0/+1
2007-09-17Actually generate SSE5 instructionsH. Peter Anvin1-1/+2
2007-09-17Initial support for four arguments per instructionH. Peter Anvin1-8/+10
2007-09-12Add (untested!) SSSE3, SSE4.1, SSE4.2 instructionsH. Peter Anvin1-0/+1
2007-09-12Remove $Id$ tags (useless with git)H. Peter Anvin1-1/+0
2007-09-12Macros for SSSE3/SSE4 instruction setsH. Peter Anvin1-0/+3
2007-09-11Make the big instruction arrays "const"H. Peter Anvin1-0/+4
2007-09-10Use an actual enum for the opcodeH. Peter Anvin1-5/+5
2007-04-17Handle "LOCK as REX.R" for MOV CRx; fix warning for invalid 64-bit regsH. Peter Anvin1-3/+5
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