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2009-06-24insns.dat: fix typos: VCMPORD_SP[SD] entered as VCMPORS_SP[SD]H. Peter Anvin1-4/+2
2009-06-24insns.dat: collapse relaxed formsH. Peter Anvin1-1212/+608
2009-05-17insns.dat - fixup for XOP (SSE5) AMD instructionsCyrill Gorcunov1-13/+23
2009-05-15insns.dat - introcuce base XOP (SSE5) AMD instructionsCyrill Gorcunov1-0/+199
2009-03-17BR 2690688: Fix opcodes for FMA instructionsH. Peter Anvin1-264/+264
2009-03-17BR 2690688: add missing VFM instructionsH. Peter Anvin1-24/+168
2009-03-16BR 2689316: PEXTRQ requires REX.WH. Peter Anvin1-1/+1
2009-03-16insns.dat: fix VFNM instructions incorrectly spelled as VFMNH. Peter Anvin1-48/+48
2009-02-23Add VPCLMUL instructionsH. Peter Anvin1-0/+12
2009-02-21PCLMUL is apparently targeted for Westmere with the AES stuffH. Peter Anvin1-6/+5
2009-02-21BR 2557903: fix disassembly of a set of SSE MOV* instructionsH. Peter Anvin1-6/+6
2009-02-21BR 2541252: Fix issues in insns.dat, mostly related to LZCNT and POPCNTH. Peter Anvin1-10/+10
2009-02-21BR 2592476: Treat WAIT as a prefix even though it's really an instructionH. Peter Anvin1-11/+10
2009-02-21Fix opcode for VADDSUBPS; operands for VBLEND; add SSE for AES opsH. Peter Anvin1-14/+14
2009-02-21FMA instructions won't be in Sandy BridgeH. Peter Anvin1-241/+240
2009-02-18Update the VFMA* instructions per the AVX spec version 5H. Peter Anvin1-64/+240
2009-02-18insns.dat: fix minor formatting anomaliesH. Peter Anvin1-3/+3
2008-12-29BR 2413278: Nonoptimal forms of arithmetic instructions involving AXH. Peter Anvin1-0/+24
2008-11-06The POPCNT instruction does not need sizes on memory operandsH. Peter Anvin1-3/+3
2008-11-06BR 2229703: POPCNT r64,rm64 not POPCNT r64,rm32H. Peter Anvin1-1/+1
2008-10-23The CRC32 instructions can take 66 prefixes as well as F2H. Peter Anvin1-5/+5
2008-10-23BR 2190521: fix the CRC32 opcodesH. Peter Anvin1-5/+5
2008-10-22BR 2187210: Fix PFRCPV and PFRSQRTVH. Peter Anvin1-2/+2
2008-10-08Reshuffle and move the bytecodes for segment register push/popH. Peter Anvin1-5/+5
2008-10-07Add missing IMUL pattern: reg64,imm8H. Peter Anvin1-0/+1
2008-10-07Add a few missing \15 -> \275 conversionsH. Peter Anvin1-6/+6
2008-10-07Change \40 class opcodes to \254, except IMULH. Peter Anvin1-12/+12
2008-10-07New opcode for 32->64 bit sign-extended immediate with warningH. Peter Anvin1-1/+1
2008-10-06New opcodes to deal with 8-bit immediate sign extended to opsizeH. Peter Anvin1-19/+19
2008-10-06Better warnings for out-of-range valuesH. Peter Anvin1-24/+0
2008-10-06BR 2148476: Fix arguments for a bunch of the CVT* instructionsH. Peter Anvin1-22/+34
2008-09-25JMP reg64 does not require a REX.W prefix.H. Peter Anvin1-1/+1
2008-08-28Accept implicit memory size for VMREAD/VMWRITEH. Peter Anvin1-4/+4
2008-08-28BR 2029472: Wrong operand size for VMREAD/VMWRITE in 64-bit modeH. Peter Anvin1-2/+4
2008-08-28BR 2028995: Missing MOVNTI m64, r64H. Peter Anvin1-1/+2
2008-08-28BR 2029829: Accept VIA XCRYPT instructions with or without REPH. Peter Anvin1-8/+9
2008-08-28BR 2039212: Handle indirect far jumps in 64-bit modeH. Peter Anvin1-2/+6
2008-08-27Add 256-bit AVX stores per the latest AVX spec.H. Peter Anvin1-2/+7
2008-08-27Add AVX forms of the AES instructions (new in the latest AVX spec)H. Peter Anvin1-0/+12
2008-08-24BR 2067820: add the MOVSXD instructionH. Peter Anvin1-1/+2
2008-08-13BR 2030823: Problem with the 256-bit FMA instructionsH. Peter Anvin1-16/+16
2008-08-13BR 2043111: Typo in insns.dat: VCMPFT_OQPD VCMPFT_OQPSH. Peter Anvin1-2/+2
2008-07-30BR 2025977: Handle SLDT with a 64-bit register operandH. Peter Anvin1-0/+2
2008-07-20BR 2023036: MOV reg32,dreg and vice versa are NOLONGH. Peter Anvin1-2/+2
2008-07-13BR 2017453: indirect jumps in 64-bit mode are implicitly 64 bitsH. Peter Anvin1-4/+4
2008-07-13Fix Bugs item #2017455 (LTR in long mode)Charles Crayne1-2/+2
2008-06-27AES instructions are WESTMERE, not NEHALEMH. Peter Anvin1-7/+6
2008-06-05The XSAVE group are SSE-spefix-sensitiveH. Peter Anvin1-5/+6
2008-05-27insns.dat: whitespace cleanupH. Peter Anvin1-1/+1
2008-05-27Fix double 66 prefixes on INVEPT/INVVPID (BR 1956955)H. Peter Anvin1-2/+2
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