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2007-10-2864-bit addressing and prefix handling changesH. Peter Anvin1-3/+3
2007-10-15Fix FISTTP opcodes (BR 689695)H. Peter Anvin1-3/+3
2007-10-02insns.dat: add systematic names for the hinting NOPs (0F18-0F1F)H. Peter Anvin1-0/+194
2007-09-25Correct the handling of "MOV" with immediate in 64-bit modeH. Peter Anvin1-3/+3
2007-09-25Fix BR 1490407: size of the second operand of LAR/LSLH. Peter Anvin1-10/+10
2007-09-24insns.dat: SMINT - mark ND, DMINT - fix opcodeH. Peter Anvin1-2/+2
2007-09-24Additional compaction missed by scriptH. Peter Anvin1-6/+3
2007-09-24insns.dat: machine-generated compaction mmx/xmmreg,mem -> mmx/xmmrmH. Peter Anvin1-506/+253
2007-09-22Implement INVLPGA according to the documentationH. Peter Anvin1-0/+3
2007-09-22Reformat insns.dat to uniform column widthH. Peter Anvin1-1864/+1864
2007-09-22Auto-generate 0x67 prefixes without the need for \30x codesH. Peter Anvin1-896/+896
2007-09-22LDDQU needs \301 (BR 1103549)H. Peter Anvin1-1/+1
2007-09-22RDTSCP and INVLPGA aren't 64-bit specificH. Peter Anvin1-2/+2
2007-09-22Cyrix GX1 instructions: BBx_RESET, CPU_READ, CPU_WRITEH. Peter Anvin1-0/+4
2007-09-22Centaur XSHA1, XSHA256, MONTMULH. Peter Anvin1-0/+3
2007-09-22Implement Centaur's XCRYPT instructionsH. Peter Anvin1-7/+13
2007-09-22Add Geode LX (AMD's Cyrix-derived core) instructionsH. Peter Anvin1-0/+6
2007-09-22Add the GETSEC instruction for Intel SMXH. Peter Anvin1-0/+3
2007-09-22Add the AMD SSE4a and LZCNT instructionsH. Peter Anvin1-0/+13
2007-09-22Tag UMOV as ND (no disassembly) to avoid collisionH. Peter Anvin1-12/+12
2007-09-18Merge commit 'origin/master' into sse5H. Peter Anvin1-0/+3
2007-09-18Add NOP with argument to the instruction listH. Peter Anvin1-0/+3
2007-09-18Implement "oword" (128 bits) as a first-class sizeH. Peter Anvin1-10/+16
2007-09-18SSE5 instruction tableH. Peter Anvin1-0/+148
2007-09-17insns.dat: All SSE5 instructions are AMDH. Peter Anvin1-16/+16
2007-09-17Actually generate SSE5 instructionsH. Peter Anvin1-0/+18
2007-09-17Merge commit 'origin/master' into sse5H. Peter Anvin1-1/+1
2007-09-17Initial support for four arguments per instructionH. Peter Anvin1-81/+81
2007-09-17CLFLUSH: Neither an x64 instruction nor AMDH. Peter Anvin1-1/+1
2007-09-12Fix literal F2 and F3 prefixesH. Peter Anvin1-64/+64
2007-09-12Add (untested!) SSSE3, SSE4.1, SSE4.2 instructionsH. Peter Anvin1-8/+80
2007-09-12Add support for Tejas New Instructions (SSSE3)H. Peter Anvin1-0/+33
2007-09-12Remove $Id$ tags (useless with git)H. Peter Anvin1-1/+0
2007-09-12Use rm32 operands for VMREAD/VMWRITEH. Peter Anvin1-4/+2
2007-09-11Handle instructions which can have both REX.W and OSPH. Peter Anvin1-2/+2
2007-09-02Fix some MMX/SSE irregularities which interact with the 64-bit supportH. Peter Anvin1-12/+12
2007-08-17Fixed issues with REX prefix effective address generation. Fixed XMM instruct...Keith Kanios1-227/+227
2007-05-30Machine-generated \321->\324 correctionsH. Peter Anvin1-148/+148
2007-05-30More \321 -> \324H. Peter Anvin1-2/+2
2007-05-30MOV reg64,reg64 takes \324 (64 bit with REX) not \321 (32 bit)H. Peter Anvin1-1/+1
2007-04-17Handle "LOCK as REX.R" for MOV CRx; fix warning for invalid 64-bit regsH. Peter Anvin1-2/+2
2007-04-16MEM_OFFSET Instructions Fixed.Keith Kanios1-4/+4
2007-04-16Fixed long mode MEM_OFFS issue.Keith Kanios1-4/+4
2007-04-16More \321 -> \324 for 64-bit instructionsH. Peter Anvin1-3/+3
2007-04-16More 64-bit ndisasm fixes.H. Peter Anvin1-2/+2
2007-04-16Fixes for 64-bit ndisasm.H. Peter Anvin1-1/+1
2007-04-15CR8 is not special in any way as far as the assembler is concerned.H. Peter Anvin1-14/+6
2007-04-12General push for x86-64 support, dubbed 0.99.00.Keith Kanios1-73/+312
2006-03-02Add VMX instructions.Eric Christopher1-0/+14
2003-09-02STR also has SMSW/SLDT-like semantics for operand sizeH. Peter Anvin1-1/+2
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