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2014-02-16BR 3392275: Don't require xmm0 to be specified when implicitH. Peter Anvin1-1/+5
BR 3392275 complains about xmm0 having to be explicitly included in the assembly syntax when it is implicit in the encoding. In the interest of "be liberal in what you accept", accept either form in the input. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-12-18mpx: Clean up instruction dataJin Kyu Song1-20/+22
Cleaned up unneccessary size specifiers in the instruction data. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-12-13insns: Mark LOADALL, LOADALL286 with ND flagCyrill Gorcunov1-2/+2
Otherwise disassembler treat syscall, sysret incorrectly. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-11-24insns.dat: Fix a typo in a commentH. Peter Anvin1-1/+1
isnsn-iflags.pl not insns-iflag.pl. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-24iflag: Move instruction flag commentH. Peter Anvin1-1/+1
Move the instruction flag comment to the Perl file where they are defined. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-24insns: Restore back MMX,FPU flagsCyrill Gorcunov1-23/+23
In commit 9bb987d8e0330429afba42015b1fc7c7ca0d1b16 we had to drop some flags due to flags type used in nasm code. Since now flags internal structure is reworked, we can restore them back. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-11-22bnd: Drop bnd prefix for relaxed short jmp instructionsJin Kyu Song1-94/+45
Reverted the redundant branch instruction patterns for bnd prefix. And when a relaxed jmp instruction becomes a short (Jb) form, bnd prefix is not needed because it does not initialize bnd registers. So in that case, bnd prefix is silently dropped. BND JMP foo -> drops bnd prefix BND JMP short foo -> shows an explicit error Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20disasm: Add basic AVX512 supportJin Kyu Song1-1/+1
Disassembler can translate EVEX prefix, count up to 32 vector registers and recognize new ZMM / opmask registers. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20PREFETCHWT1: Add a new instruction flagJin Kyu Song1-1/+1
PREFETCHWT1 instruction's CPUID was TBD before. Now it has its new CPUID bit : PREFETCHWT1 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20AVX512: Update instruction groupJin Kyu Song1-2/+2
CPUID bit for vptestnm[dq] changed. vptestnm[dq]: AVX512CD -> AVX512F Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Move BND prefix indication from bytecode to iflagsJin Kyu Song1-46/+45
As BND prefix validity check conflicts with jcc8 prefix, IF_BND is added for the instruction templates which can have bnd prefix for preserving the content of bound register. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20SHA: Add SHA instructionsJin Kyu Song1-0/+9
New instruction extensions of SHA family are added. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Add BND prefix for branch instructionsJin Kyu Song1-0/+54
BND prefix is used for adding bounds checking protection across flow control changes such as call, ret, jmp and jcc calls. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Add MPX instructionsJin Kyu Song1-0/+21
Added MPX instructions and corresponding parser and encoder. ICC style mib - base + disp and index are separate - is supported. E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index As a supplement to NASM style mib - split EA - parser, omitted base+disp is now treated as 0 displacement. E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-10-02Add support for DZ and RESZ, document the ZWORD keywordH. Peter Anvin1-0/+2
Add the DZ and RESZ pseudoinstructions and add ZWORD to the documentation. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-09-14AVX-512: Added AVX-512PF instructionsJin Kyu Song1-0/+18
Added Prefetch (AVX-512PF) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512PF[bit 26] = 1. CPUID feature flag for PREFETCHWT1 is TBD but PREFETCHWT1 is included in this commit. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-09-14AVX-512: Add AVX-512ER instructionsJin Kyu Song1-0/+11
Added Exponential and Reciprocal (AVX-512ER) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512ER[bit 27] = 1. IF_AVX512 is now shared by all AVX-512* instructions as a bit mask. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-09-14AVX-512: Add AVX-512CD instructionsJin Kyu Song1-0/+10
Added Conflict Detection (AVX-512CD) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512CD[bit 28] = 1. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-09-07AVX-512: Add Pseudo-ops for CMP instructionsJin Kyu Song1-0/+150
Added three-operand pseudo-ops for VCMPPD, VPCMPD and so on. Test case is also updated to validate them. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-09-07AVX-512: Reorder instructions in insns.datJin Kyu Song1-57/+57
Within a same instruction mnemonic, instructions are reordered in order of opcode byte value. Therefore when there are two possible opcode candidates, smaller opcode is picked now. e.g.) vmovapd zmm30, zmm29 -> now 28h is used. 29h previously Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-29AVX-512: Add OPMASK instructionsJin Kyu Song1-14/+30
Added opmask instructions (kandw and etc). Defined KREG and RM_K aliasing RM_OPMASK and OPMASKREG respectively to make insns.dat look neat. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-28AVX-512: Change the data type for instruction flagsJin Kyu Song1-23/+23
Increased the size of data type for instruction flags from 32bits to 64bits. And a new type (iflags_t) is defined for better maintainability. Bigger data type is needed because more instruction set types are coming but there were not enough space for them. Since they are not bit masks, only one instruction set is allowed for each instruction. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-28AVX-512: Moved {er} decorator position next to the last SIMD opJin Kyu Song1-8/+9
This is for following the current syntax used in gas even though this is not SDM conforming. According to SDM, {er} should follow the last GPR op not SIMD op. e.g. SDM : VCVTSI2SD xmm1, xmm2, r/m64{er} NASM : VCVTSI2SD xmm1, xmm2{er}, r/m64 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-16AVX-512: Add EVEX encoding and new instructionsJin Kyu Song1-9/+439
EVEX encoding support includes 32 vector regs (XMM/YMM/ZMM), opmask, broadcasting, embedded rounding mode, suppress all exceptions, compressed displacement. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-07-21insns: Fix MOVLPDCyrill Gorcunov1-2/+2
http://bugzilla.nasm.us/show_bug.cgi?id=978756 Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-07-21insns: Fix MOVNTDQA instructionCyrill Gorcunov1-1/+1
http://bugzilla.nasm.us/show_bug.cgi?id=3392259 Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-07-21insns: Fix VMOVNTDQA instructionCyrill Gorcunov1-1/+1
http://bugzilla.nasm.us/show_bug.cgi?id=3392259 Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-07-19BR 3392260: Handle instructions only separated by vector SIB sizeH. Peter Anvin1-19/+19
There are two instructions (VGATHERQPS, VPGATHERQD) where the only separation between two forms is the vector length given to the vector SIB. This means the *matcher* has to be able to distinguish instructions by vector SIB length and the matcher only operates on the operands and the instruction flags, not on the bytecode. Export the vector index-ness into the operand flags and add to the matcher. This resolves BR 3392260. Reported-by: Agner <agner@anger.org> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-06-30insns: Fix vspllw instructionMITSUNARI Shigeo1-1/+1
http://bugzilla.nasm.us/show_bug.cgi?id=3392257 Signed-off-by: MITSUNARI Shigeo <herumi@nifty.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-06-01insns: Fix vgatherqpd instructionMITSUNARI Shigeo1-1/+1
Signed-off-by: MITSUNARI Shigeo <herumi@nifty.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-24insns: Fix VPMOVSXBQ instructionMITSUNARI Shigeo1-1/+1
http://bugzilla.nasm.us/show_bug.cgi?id=3392254 Signed-off-by: MITSUNARI Shigeo <herumi@nifty.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-12insns.dat: Add note about AMD TBM instructionsCyrill Gorcunov1-1/+1
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-12insns.dat: Add BLCMSKCyrill Gorcunov1-0/+2
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-12insns.dat: Add BLCSCyrill Gorcunov1-0/+2
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-12insns.dat: Add BLSFILLCyrill Gorcunov1-0/+2
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-12insns.dat: Add BLCFILLCyrill Gorcunov1-0/+2
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-12insns.dat: Add BLCICCyrill Gorcunov1-0/+2
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-12insns.dat: Add BLCICyrill Gorcunov1-0/+2
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-12insns.dat: Add BLSICCyrill Gorcunov1-0/+2
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-12insns.dat: Add immediate form of BEXTRCyrill Gorcunov1-0/+2
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-12insns.dat: Add T1MSKC intstructionCyrill Gorcunov1-1/+3
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-12insns.dat: Add TZMSK instructionCyrill Gorcunov1-0/+2
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-12insns.dat: Move TZCNT for alphabetical orderCyrill Gorcunov1-3/+3
Other instructions in this section already sorted. No func changes. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-04insns.dat: Udate yearCyrill Gorcunov1-1/+1
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-04br3392250: insns -- Allow byte size in PREFETCHTx instructionsCyrill Gorcunov1-4/+4
The PREFETCHTx instructions do allow mem8 (byte). Reported-by: Agner <agner@agner.org> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-03insns: Remove pushseg/popseg internal bytecodesBen Rudiak-Gould1-5/+11
This patch is getting rid of the following bytecodes 'pushseg','popseg','pushseg2','popseg2' and simplifies overall code. [gorcunov@: a few style fixes] Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-01Remove +sBen Rudiak-Gould1-128/+173
It doesn't seem worth >200 lines of C and Perl to save ~50 lines in insns.dat. In order to make this work I had to rename sbyte16/sbyte32 so that they can take an ordinary size suffix (their size suffix was formerly treated specially). This fixes one disassembly bug: 48C7C000000080 disassembles to mov rax,0x80000000, which reassembles to B800000080, which loads a different value. Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Acked-by: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-02-21BR3392242: insns.dat -- Support AMD SVM instructions in 32bit modeAndrew Nayenko1-7/+7
AMD CPUs do support SVM instructions in 32-bit mode thus drop X64 restriction from instructions template where appropriate. Signed-off-by: Andrew Nayenko <resver@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-02-20Fix jmp/call near offsets in long modeBen Rudiak-Gould1-36/+37
In long mode relative offsets are always 32 bits sign-extended to 64 bits and absolute near addresses are always 64 bits, regardless of the operand size. Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-02-20Add np and similar prefixes to instructions that should have themBen Rudiak-Gould1-56/+56
This adds "np" to a bunch of SSE-style instructions that should have it, "norep" (which was implemented but unused) on quasi-SSE instructions that use F2 and F3 as instruction extensions but 66 for operand size, "nof3" (newly implemented) on a few instructions, "norexw" on some instructions that have only 32-bit and 64-bit versions, and one NOLONG. It also removes some incorrect "np"s, changes some "f3"s to "f3i"s, and fixes the decoding of the XCHG/NOP/PAUSE mess: F390 is always PAUSE even when rex.b=1 (at least according to XED). Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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