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AgeCommit message (Expand)AuthorFilesLines
2008-04-04Correctly identify SBYTE in the optimizerH. Peter Anvin1-49/+48
2008-03-22Remove KATMAI support for CLFLUSHCharles Crayne1-1/+0
2008-03-19insns.dat: add "MOV reg64,imm32" as a special ruleH. Peter Anvin1-0/+1
2008-03-18Correct opcode for CLFLUSHCharles Crayne1-1/+1
2008-02-16BR 1893952: XGETBV is not privileged.H. Peter Anvin1-2/+2
2008-02-14Add XSAVE instruction features (CPU feature is bogus, but oh well.)H. Peter Anvin1-0/+7
2008-01-30BR 1879590: More MMX/SSE size fixesIsmail Dönmez1-199/+199
2008-01-20Add autogenerated instruction list to NASM documentationCharles Crayne1-22/+26
2007-12-29regularized spelling of license to match name of LICENSE fileBeroset1-1/+1
2007-12-25Remove bogus duplicates of the PREFETCH* instructionsH. Peter Anvin1-4/+0
2007-12-25(Hopefully) fix the handing of MMX instructions with prefixesH. Peter Anvin1-80/+80
2007-11-20Unbreak CMPSW/CMPSD/CMPSQH. Peter Anvin1-3/+3
2007-11-18BR 1834292: Fix multiple disassembler bugsH. Peter Anvin1-59/+59
2007-11-15BR 993895: Support zero-operand floating-point insnH. Peter Anvin1-3/+36
2007-11-12Un-special-case "xchg rax,rax"; disassemble o64H. Peter Anvin1-4/+5
2007-11-12BR 1828866: fix handling of LAR/LSLH. Peter Anvin1-0/+12
2007-11-12Fix disassembly of XCHGH. Peter Anvin1-1/+1
2007-11-12Fix handling of XCHG in 64-bit modeH. Peter Anvin1-5/+8
2007-11-12More \321 -> \324 bug fixesH. Peter Anvin1-17/+17
2007-10-2864-bit addressing and prefix handling changesH. Peter Anvin1-3/+3
2007-10-15Fix FISTTP opcodes (BR 689695)H. Peter Anvin1-3/+3
2007-10-02insns.dat: add systematic names for the hinting NOPs (0F18-0F1F)H. Peter Anvin1-0/+194
2007-09-25Correct the handling of "MOV" with immediate in 64-bit modeH. Peter Anvin1-3/+3
2007-09-25Fix BR 1490407: size of the second operand of LAR/LSLH. Peter Anvin1-10/+10
2007-09-24insns.dat: SMINT - mark ND, DMINT - fix opcodeH. Peter Anvin1-2/+2
2007-09-24Additional compaction missed by scriptH. Peter Anvin1-6/+3
2007-09-24insns.dat: machine-generated compaction mmx/xmmreg,mem -> mmx/xmmrmH. Peter Anvin1-506/+253
2007-09-22Implement INVLPGA according to the documentationH. Peter Anvin1-0/+3
2007-09-22Reformat insns.dat to uniform column widthH. Peter Anvin1-1864/+1864
2007-09-22Auto-generate 0x67 prefixes without the need for \30x codesH. Peter Anvin1-896/+896
2007-09-22LDDQU needs \301 (BR 1103549)H. Peter Anvin1-1/+1
2007-09-22RDTSCP and INVLPGA aren't 64-bit specificH. Peter Anvin1-2/+2
2007-09-22Cyrix GX1 instructions: BBx_RESET, CPU_READ, CPU_WRITEH. Peter Anvin1-0/+4
2007-09-22Centaur XSHA1, XSHA256, MONTMULH. Peter Anvin1-0/+3
2007-09-22Implement Centaur's XCRYPT instructionsH. Peter Anvin1-7/+13
2007-09-22Add Geode LX (AMD's Cyrix-derived core) instructionsH. Peter Anvin1-0/+6
2007-09-22Add the GETSEC instruction for Intel SMXH. Peter Anvin1-0/+3
2007-09-22Add the AMD SSE4a and LZCNT instructionsH. Peter Anvin1-0/+13
2007-09-22Tag UMOV as ND (no disassembly) to avoid collisionH. Peter Anvin1-12/+12
2007-09-18Merge commit 'origin/master' into sse5H. Peter Anvin1-0/+3
2007-09-18Add NOP with argument to the instruction listH. Peter Anvin1-0/+3
2007-09-18Implement "oword" (128 bits) as a first-class sizeH. Peter Anvin1-10/+16
2007-09-18SSE5 instruction tableH. Peter Anvin1-0/+148
2007-09-17insns.dat: All SSE5 instructions are AMDH. Peter Anvin1-16/+16
2007-09-17Actually generate SSE5 instructionsH. Peter Anvin1-0/+18
2007-09-17Merge commit 'origin/master' into sse5H. Peter Anvin1-1/+1
2007-09-17Initial support for four arguments per instructionH. Peter Anvin1-81/+81
2007-09-17CLFLUSH: Neither an x64 instruction nor AMDH. Peter Anvin1-1/+1
2007-09-12Fix literal F2 and F3 prefixesH. Peter Anvin1-64/+64
2007-09-12Add (untested!) SSSE3, SSE4.1, SSE4.2 instructionsH. Peter Anvin1-8/+80
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