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2014-02-19Add CLFLUSHOPT instructionH. Peter Anvin1-0/+3
2014-02-19insns: add XSAVEC, XSAVES and XRSTORS instructionsH. Peter Anvin1-0/+6
2014-02-16BR 3392275: Don't require xmm0 to be specified when implicitH. Peter Anvin1-1/+5
2013-12-18mpx: Clean up instruction dataJin Kyu Song1-20/+22
2013-12-13insns: Mark LOADALL, LOADALL286 with ND flagCyrill Gorcunov1-2/+2
2013-11-24insns.dat: Fix a typo in a commentH. Peter Anvin1-1/+1
2013-11-24iflag: Move instruction flag commentH. Peter Anvin1-1/+1
2013-11-24insns: Restore back MMX,FPU flagsCyrill Gorcunov1-23/+23
2013-11-22bnd: Drop bnd prefix for relaxed short jmp instructionsJin Kyu Song1-94/+45
2013-11-20disasm: Add basic AVX512 supportJin Kyu Song1-1/+1
2013-11-20PREFETCHWT1: Add a new instruction flagJin Kyu Song1-1/+1
2013-11-20AVX512: Update instruction groupJin Kyu Song1-2/+2
2013-11-20MPX: Move BND prefix indication from bytecode to iflagsJin Kyu Song1-46/+45
2013-11-20SHA: Add SHA instructionsJin Kyu Song1-0/+9
2013-11-20MPX: Add BND prefix for branch instructionsJin Kyu Song1-0/+54
2013-11-20MPX: Add MPX instructionsJin Kyu Song1-0/+21
2013-10-02Add support for DZ and RESZ, document the ZWORD keywordH. Peter Anvin1-0/+2
2013-09-14AVX-512: Added AVX-512PF instructionsJin Kyu Song1-0/+18
2013-09-14AVX-512: Add AVX-512ER instructionsJin Kyu Song1-0/+11
2013-09-14AVX-512: Add AVX-512CD instructionsJin Kyu Song1-0/+10
2013-09-07AVX-512: Add Pseudo-ops for CMP instructionsJin Kyu Song1-0/+150
2013-09-07AVX-512: Reorder instructions in insns.datJin Kyu Song1-57/+57
2013-08-29AVX-512: Add OPMASK instructionsJin Kyu Song1-14/+30
2013-08-28AVX-512: Change the data type for instruction flagsJin Kyu Song1-23/+23
2013-08-28AVX-512: Moved {er} decorator position next to the last SIMD opJin Kyu Song1-8/+9
2013-08-16AVX-512: Add EVEX encoding and new instructionsJin Kyu Song1-9/+439
2013-07-21insns: Fix MOVLPDCyrill Gorcunov1-2/+2
2013-07-21insns: Fix MOVNTDQA instructionCyrill Gorcunov1-1/+1
2013-07-21insns: Fix VMOVNTDQA instructionCyrill Gorcunov1-1/+1
2013-07-19BR 3392260: Handle instructions only separated by vector SIB sizeH. Peter Anvin1-19/+19
2013-06-30insns: Fix vspllw instructionMITSUNARI Shigeo1-1/+1
2013-06-01insns: Fix vgatherqpd instructionMITSUNARI Shigeo1-1/+1
2013-05-24insns: Fix VPMOVSXBQ instructionMITSUNARI Shigeo1-1/+1
2013-05-12insns.dat: Add note about AMD TBM instructionsCyrill Gorcunov1-1/+1
2013-05-12insns.dat: Add BLCMSKCyrill Gorcunov1-0/+2
2013-05-12insns.dat: Add BLCSCyrill Gorcunov1-0/+2
2013-05-12insns.dat: Add BLSFILLCyrill Gorcunov1-0/+2
2013-05-12insns.dat: Add BLCFILLCyrill Gorcunov1-0/+2
2013-05-12insns.dat: Add BLCICCyrill Gorcunov1-0/+2
2013-05-12insns.dat: Add BLCICyrill Gorcunov1-0/+2
2013-05-12insns.dat: Add BLSICCyrill Gorcunov1-0/+2
2013-05-12insns.dat: Add immediate form of BEXTRCyrill Gorcunov1-0/+2
2013-05-12insns.dat: Add T1MSKC intstructionCyrill Gorcunov1-1/+3
2013-05-12insns.dat: Add TZMSK instructionCyrill Gorcunov1-0/+2
2013-05-12insns.dat: Move TZCNT for alphabetical orderCyrill Gorcunov1-3/+3
2013-05-04insns.dat: Udate yearCyrill Gorcunov1-1/+1
2013-05-04br3392250: insns -- Allow byte size in PREFETCHTx instructionsCyrill Gorcunov1-4/+4
2013-03-03insns: Remove pushseg/popseg internal bytecodesBen Rudiak-Gould1-5/+11
2013-03-01Remove +sBen Rudiak-Gould1-128/+173
2013-02-21BR3392242: insns.dat -- Support AMD SVM instructions in 32bit modeAndrew Nayenko1-7/+7
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