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2008-10-23The CRC32 instructions can take 66 prefixes as well as F2H. Peter Anvin1-5/+5
2008-10-23BR 2190521: fix the CRC32 opcodesH. Peter Anvin1-5/+5
2008-10-22BR 2187210: Fix PFRCPV and PFRSQRTVH. Peter Anvin1-2/+2
2008-10-08Reshuffle and move the bytecodes for segment register push/popH. Peter Anvin1-5/+5
2008-10-07Add missing IMUL pattern: reg64,imm8H. Peter Anvin1-0/+1
2008-10-07Add a few missing \15 -> \275 conversionsH. Peter Anvin1-6/+6
2008-10-07Change \40 class opcodes to \254, except IMULH. Peter Anvin1-12/+12
2008-10-07New opcode for 32->64 bit sign-extended immediate with warningH. Peter Anvin1-1/+1
2008-10-06New opcodes to deal with 8-bit immediate sign extended to opsizeH. Peter Anvin1-19/+19
2008-10-06Better warnings for out-of-range valuesH. Peter Anvin1-24/+0
2008-10-06BR 2148476: Fix arguments for a bunch of the CVT* instructionsH. Peter Anvin1-22/+34
2008-09-25JMP reg64 does not require a REX.W prefix.H. Peter Anvin1-1/+1
2008-08-28Accept implicit memory size for VMREAD/VMWRITEH. Peter Anvin1-4/+4
2008-08-28BR 2029472: Wrong operand size for VMREAD/VMWRITE in 64-bit modeH. Peter Anvin1-2/+4
2008-08-28BR 2028995: Missing MOVNTI m64, r64H. Peter Anvin1-1/+2
2008-08-28BR 2029829: Accept VIA XCRYPT instructions with or without REPH. Peter Anvin1-8/+9
2008-08-28BR 2039212: Handle indirect far jumps in 64-bit modeH. Peter Anvin1-2/+6
2008-08-27Add 256-bit AVX stores per the latest AVX spec.H. Peter Anvin1-2/+7
2008-08-27Add AVX forms of the AES instructions (new in the latest AVX spec)H. Peter Anvin1-0/+12
2008-08-24BR 2067820: add the MOVSXD instructionH. Peter Anvin1-1/+2
2008-08-13BR 2030823: Problem with the 256-bit FMA instructionsH. Peter Anvin1-16/+16
2008-08-13BR 2043111: Typo in insns.dat: VCMPFT_OQPD VCMPFT_OQPSH. Peter Anvin1-2/+2
2008-07-30BR 2025977: Handle SLDT with a 64-bit register operandH. Peter Anvin1-0/+2
2008-07-20BR 2023036: MOV reg32,dreg and vice versa are NOLONGH. Peter Anvin1-2/+2
2008-07-13BR 2017453: indirect jumps in 64-bit mode are implicitly 64 bitsH. Peter Anvin1-4/+4
2008-07-13Fix Bugs item #2017455 (LTR in long mode)Charles Crayne1-2/+2
2008-06-27AES instructions are WESTMERE, not NEHALEMH. Peter Anvin1-7/+6
2008-06-05The XSAVE group are SSE-spefix-sensitiveH. Peter Anvin1-5/+6
2008-05-27insns.dat: whitespace cleanupH. Peter Anvin1-1/+1
2008-05-27Fix double 66 prefixes on INVEPT/INVVPID (BR 1956955)H. Peter Anvin1-2/+2
2008-05-26VCVTPD2PS, VCVTPD2DQ, VCVTTPD2DQ mem need explicit op size (BR 1974170)H. Peter Anvin1-6/+12
2008-05-26Fix parameters to VCVTPD2DQ (BR 1974159)H. Peter Anvin1-1/+1
2008-05-25Fix mnemnonics for SSE5 PCOMU instructionsH. Peter Anvin1-32/+32
2008-05-24Fix mnemonics for VTESTP[SD] (BR 1971570)H. Peter Anvin1-4/+4
2008-05-24Fix the VPSHUF*W instructions (BR 1971567)H. Peter Anvin1-2/+2
2008-05-24Fix typo in VPCMPESTRM instruction (BR 1971565)H. Peter Anvin1-1/+1
2008-05-24Add VCVTSI2SS (BR 1971564)H. Peter Anvin1-0/+4
2008-05-24Fix immediate for PCLMULHQ* instructions (BR 1971555)H. Peter Anvin1-2/+2
2008-05-24Remove imm from specific versions of VCMPxxH. Peter Anvin1-384/+384
2008-05-24Add VLDQQU as an alias for 256-bit VLDDQU (BR 1971539)H. Peter Anvin1-0/+1
2008-05-24VFMSUBADDP[SD], not VFMADDSUBS[SD] (BR 1971573)H. Peter Anvin1-4/+8
2008-05-23AVX FMA: Instruction table for the AVX FMA instructionsH. Peter Anvin1-0/+63
2008-05-23AVX: Remaining AVX instructions (still need FMA)H. Peter Anvin1-0/+73
2008-05-23AVX instruction table through "P"H. Peter Anvin1-0/+172
2008-05-21AVX: instruction table up to PEH. Peter Anvin1-8/+112
2008-05-21AVX: instruction table through MH. Peter Anvin1-8/+105
2008-05-21Implement aliases for specific SSE5 compare operationsH. Peter Anvin1-4/+144
2008-05-21insns.dat: reimplement SSE5 compares using the bytecode compilerH. Peter Anvin1-12/+12
2008-05-21Add the PCLMUL instructions (BR 1933742)H. Peter Anvin1-0/+8
2008-05-21Add INVEPT and INVVPID (BR 1956955)H. Peter Anvin1-0/+5
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