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2011-06-22Add support for VSIB instructionsH. Peter Anvin1-5/+27
2010-09-12BR3064376: ndisasm crashCyrill Gorcunov1-1/+1
2010-08-19ndisasm: handle VEX.LIGH. Peter Anvin1-1/+1
2010-08-19ndisasm: unify VEX handlingH. Peter Anvin1-34/+6
2010-08-16ndisasm: fix handing of byte codes 250-253, 324H. Peter Anvin1-2/+12
2010-08-16assemble: handle vex.ligH. Peter Anvin1-5/+7
2009-10-18continue using is_class helperCyrill Gorcunov1-2/+2
2009-10-13opflags: more int32_t -> opflags_t conversionsH. Peter Anvin1-1/+1
2009-08-09disasm.c: eatbyte -- use snprintf to prevent potential buffer overflowCyrill Gorcunov1-1/+1
2009-07-06NASM: relicense under the 2-clause BSD licenseH. Peter Anvin1-12/+0
2009-06-28Add copyright headers to the *.c/*.h files in the main directoryH. Peter Anvin1-6/+45
2009-06-26ndisasm: fix disassembly of JRCXZH. Peter Anvin1-1/+1
2009-06-24Add support for instructions which always use low 8-bit registersH. Peter Anvin1-2/+6
2009-05-08Add symbolic constants for REX_V "classes" (VEX, XOP, ...)H. Peter Anvin1-4/+4
2009-05-03Use lower case for VEX and XOP in instructions tableH. Peter Anvin1-2/+2
2009-05-03Infrastructure support for AMD's new XOP prefixH. Peter Anvin1-1/+24
2009-03-19disasm: fix reversed REP vs REPNE in eatbyte()H. Peter Anvin1-2/+2
2009-03-18disasm: when no instruction is found, consider a naked prefixH. Peter Anvin1-2/+80
2009-02-21BR 2592476: Treat WAIT as a prefix even though it's really an instructionH. Peter Anvin1-35/+20
2008-10-25disasm: introduce opyH. Peter Anvin1-3/+4
2008-10-23disasm: extension byte support in the disassemblerH. Peter Anvin1-12/+20
2008-10-23Add extension bytecodes to support operands 4+H. Peter Anvin1-0/+1
2008-10-09disasm: collapse all the segment register push/pop bytecodesH. Peter Anvin1-59/+2
2008-10-08Reshuffle and move the bytecodes for segment register push/popH. Peter Anvin1-61/+61
2008-10-07New opcode for 32->64 bit sign-extended immediate with warningH. Peter Anvin1-0/+1
2008-10-06New opcodes to deal with 8-bit immediate sign extended to opsizeH. Peter Anvin1-0/+1
2008-08-28BR 2029829: Accept VIA XCRYPT instructions with or without REPH. Peter Anvin1-0/+4
2008-08-20BR 2062342: ndisasm: r12 *can* be an index registerH. Peter Anvin1-2/+2
2008-07-30BR 2028910: fix decoding of VEX prefixes in 16- and 32-bit modeH. Peter Anvin1-16/+17
2008-05-26ndisasm: the high bit of is4 bytes is ignored in 32-bit modeH. Peter Anvin1-3/+4
2008-05-22Add tokens vex.ww and vex.wx; vex.wx is the defaultH. Peter Anvin1-2/+6
2008-05-21insnsn.c: cleaner to *not* separate out conditional instructionsH. Peter Anvin1-5/+4
2008-05-21Disassembler: select table based on VEX prefixesH. Peter Anvin1-1/+14
2008-05-21Fix display for fixed xmm0/ymm0, SSE redundant prefixesH. Peter Anvin1-0/+7
2008-05-20VEX prefixes apply to VEX instructions only...H. Peter Anvin1-0/+6
2008-05-20Handle is4 bytes without meaningful information in the bottom bitsH. Peter Anvin1-0/+10
2008-05-20ndisasm: simple compare for conditional opcodes, no loopH. Peter Anvin1-12/+9
2008-05-20Avoid #including .c files; instead compile as separate unitsH. Peter Anvin1-46/+40
2008-05-20Add DY, YWORD, and the SY instruction flagH. Peter Anvin1-0/+3
2008-05-20Same some space by introducing shorthand byte codes for SSE prefixesH. Peter Anvin1-0/+20
2008-05-12Remove special hacks to avoid zero bytecodesH. Peter Anvin1-5/+0
2008-05-06Add support for register-number immediates with fixed 4-bit valuesH. Peter Anvin1-0/+13
2008-05-05Initial NDISASM support for AVX instructions/VEX prefixesH. Peter Anvin1-9/+121
2008-05-04First cut at AVX machinery.H. Peter Anvin1-0/+10
2008-01-02disasm: relative operands are signed, not unsignedH. Peter Anvin1-4/+7
2007-12-29regularized spelling of license to match name of LICENSE fileBeroset1-1/+1
2007-12-26disasm: 32-bit index registers were displayed as 64 bitsH. Peter Anvin1-1/+1
2007-11-18BR 1834292: Fix multiple disassembler bugsH. Peter Anvin1-4/+23
2007-11-13Address data is int64_t; simplify writing an address objectH. Peter Anvin1-1/+1
2007-11-12ndisasm: factor out the common operand-extraction codeH. Peter Anvin1-38/+41
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