| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2008-10-23 | disasm: extension byte support in the disassembler | H. Peter Anvin | 1 | -12/+20 |
| 2008-10-23 | Add extension bytecodes to support operands 4+ | H. Peter Anvin | 1 | -0/+1 |
| 2008-10-09 | disasm: collapse all the segment register push/pop bytecodes | H. Peter Anvin | 1 | -59/+2 |
| 2008-10-08 | Reshuffle and move the bytecodes for segment register push/pop | H. Peter Anvin | 1 | -61/+61 |
| 2008-10-07 | New opcode for 32->64 bit sign-extended immediate with warning | H. Peter Anvin | 1 | -0/+1 |
| 2008-10-06 | New opcodes to deal with 8-bit immediate sign extended to opsize | H. Peter Anvin | 1 | -0/+1 |
| 2008-08-28 | BR 2029829: Accept VIA XCRYPT instructions with or without REP | H. Peter Anvin | 1 | -0/+4 |
| 2008-08-20 | BR 2062342: ndisasm: r12 *can* be an index register | H. Peter Anvin | 1 | -2/+2 |
| 2008-07-30 | BR 2028910: fix decoding of VEX prefixes in 16- and 32-bit mode | H. Peter Anvin | 1 | -16/+17 |
| 2008-05-26 | ndisasm: the high bit of is4 bytes is ignored in 32-bit mode | H. Peter Anvin | 1 | -3/+4 |
| 2008-05-22 | Add tokens vex.ww and vex.wx; vex.wx is the default | H. Peter Anvin | 1 | -2/+6 |
| 2008-05-21 | insnsn.c: cleaner to *not* separate out conditional instructions | H. Peter Anvin | 1 | -5/+4 |
| 2008-05-21 | Disassembler: select table based on VEX prefixes | H. Peter Anvin | 1 | -1/+14 |
| 2008-05-21 | Fix display for fixed xmm0/ymm0, SSE redundant prefixes | H. Peter Anvin | 1 | -0/+7 |
| 2008-05-20 | VEX prefixes apply to VEX instructions only... | H. Peter Anvin | 1 | -0/+6 |
| 2008-05-20 | Handle is4 bytes without meaningful information in the bottom bits | H. Peter Anvin | 1 | -0/+10 |
| 2008-05-20 | ndisasm: simple compare for conditional opcodes, no loop | H. Peter Anvin | 1 | -12/+9 |
| 2008-05-20 | Avoid #including .c files; instead compile as separate units | H. Peter Anvin | 1 | -46/+40 |
| 2008-05-20 | Add DY, YWORD, and the SY instruction flag | H. Peter Anvin | 1 | -0/+3 |
| 2008-05-20 | Same some space by introducing shorthand byte codes for SSE prefixes | H. Peter Anvin | 1 | -0/+20 |
| 2008-05-12 | Remove special hacks to avoid zero bytecodes | H. Peter Anvin | 1 | -5/+0 |
| 2008-05-06 | Add support for register-number immediates with fixed 4-bit values | H. Peter Anvin | 1 | -0/+13 |
| 2008-05-05 | Initial NDISASM support for AVX instructions/VEX prefixes | H. Peter Anvin | 1 | -9/+121 |
| 2008-05-04 | First cut at AVX machinery. | H. Peter Anvin | 1 | -0/+10 |
| 2008-01-02 | disasm: relative operands are signed, not unsigned | H. Peter Anvin | 1 | -4/+7 |
| 2007-12-29 | regularized spelling of license to match name of LICENSE file | Beroset | 1 | -1/+1 |
| 2007-12-26 | disasm: 32-bit index registers were displayed as 64 bits | H. Peter Anvin | 1 | -1/+1 |
| 2007-11-18 | BR 1834292: Fix multiple disassembler bugs | H. Peter Anvin | 1 | -4/+23 |
| 2007-11-13 | Address data is int64_t; simplify writing an address object | H. Peter Anvin | 1 | -1/+1 |
| 2007-11-12 | ndisasm: factor out the common operand-extraction code | H. Peter Anvin | 1 | -38/+41 |
| 2007-11-12 | Un-special-case "xchg rax,rax"; disassemble o64 | H. Peter Anvin | 1 | -5/+30 |
| 2007-11-12 | Better (but not *good!*) handling of 64-bit addressing in ndisasm | H. Peter Anvin | 1 | -97/+269 |
| 2007-11-12 | Fix disassembly of XCHG | H. Peter Anvin | 1 | -0/+12 |
| 2007-10-28 | 64-bit addressing and prefix handling changes | H. Peter Anvin | 1 | -26/+42 |
| 2007-10-23 | Fix bugs item #1817677 | Charles Crayne | 1 | -0/+1 |
| 2007-10-19 | Formatting: kill off "stealth whitespace" | H. Peter Anvin | 1 | -3/+3 |
| 2007-10-18 | Suppress signedness warnings in disassembler | Charles Crayne | 1 | -1/+1 |
| 2007-10-10 | Use the compiler-provided booleans if available, otherwise emulate | H. Peter Anvin | 1 | -48/+48 |
| 2007-10-02 | Portability fixes | H. Peter Anvin | 1 | -0/+2 |
| 2007-09-22 | Auto-generate 0x67 prefixes without the need for \30x codes | H. Peter Anvin | 1 | -2/+5 |
| 2007-09-18 | Speed up the disassembler by allowing prefixed instruction tables | H. Peter Anvin | 1 | -2/+11 |
| 2007-09-17 | Disassembler support for SSE5 instructions | H. Peter Anvin | 1 | -76/+131 |
| 2007-09-17 | Initial support for four arguments per instruction | H. Peter Anvin | 1 | -27/+27 |
| 2007-09-12 | Add (untested!) SSSE3, SSE4.1, SSE4.2 instructions | H. Peter Anvin | 1 | -3/+6 |
| 2007-09-12 | Support r/m operands for non-integer types | H. Peter Anvin | 1 | -4/+9 |
| 2007-09-11 | Handle instructions which can have both REX.W and OSP | H. Peter Anvin | 1 | -52/+71 |
| 2007-09-11 | ndisasm: handle \366 codes, prefer unprefixed instructions | H. Peter Anvin | 1 | -12/+34 |
| 2007-09-11 | Quiet gcc warning about uninitialized variables | H. Peter Anvin | 1 | -0/+2 |
| 2007-09-11 | Make the big instruction arrays "const" | H. Peter Anvin | 1 | -4/+2 |
| 2007-08-28 | Implement REL/ABS modifiers | H. Peter Anvin | 1 | -9/+14 |
