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2014-05-21BR 3392279: Fix duplicated REX prefixesH. Peter Anvin1-2/+7
The fix for BR 3392278: aa29b1d93f5a assemble.c: Don't drop rex prefix from instruction itself ... would cause multiple REX prefixes to be emitted for some instructions. Create a new flag to indicate that REX has already been emitted, which can be cleared for each instance of an instruction. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2014-05-05AVX512: Remove invalid error checkingJin Kyu Song1-3/+0
An offset-only memref can also have an opmask decorator. e.g.) vmovdqu32 [0xabcd]{k1}, zmm0 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2014-05-05assemble.c: Don't drop rex prefix from instruction itselfCyrill Gorcunov1-3/+2
emit_rex is supposed to write REX prefix into output stream if needed, but we happen to drop it off on a first write which breaks REX required instructions if TIMES directive is used. For example the code like | times 4 movq xmm11, xmm11 compiles into | 0000000000000000 <.text>: | 0: f3 45 0f 7e db movq %xmm11,%xmm11 | 5: f3 0f 7e db movq %xmm3,%xmm3 | 9: f3 0f 7e db movq %xmm3,%xmm3 | d: f3 0f 7e db movq %xmm3,%xmm3 instead of proper | 0000000000000000 <.text>: | 0: f3 45 0f 7e db movq %xmm11,%xmm11 | 5: f3 45 0f 7e db movq %xmm11,%xmm11 | a: f3 45 0f 7e db movq %xmm11,%xmm11 | f: f3 45 0f 7e db movq %xmm11,%xmm11 http://bugzilla.nasm.us/show_bug.cgi?id=3392278 Reported-by: Javier <elpochodelagente@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-12-18nosplit: Generate index-only EA only when a multiplier is used.Jin Kyu Song1-2/+3
[nosplit eax] has been encoded as [eax*1+0] since 0.98.34. But this seems like unexpected behavior. So only when a register is multiplied, that will be treated as an index. ([nosplit eax*1] -> [eax*1+0]) Document is updated accordingly. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-12-18nosplit: Limit the effect of NOSPLITJin Kyu Song1-1/+1
[nosplit eax+eax] was encoded [eax*2] previously but this seems against the user's intention. So in this case, nosplit is ignored now and [eax+eax] will be generated. Document is also updated accordingly. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-12-18mib: Avoid RIP-relative addressing in mibJin Kyu Song1-0/+6
Using RIP relative for mib operands causes #UD exception. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-12-11mib: Handle MIB EA in a different way from regular EA'sJin Kyu Song1-36/+49
In mib operands, users' intention should be preserved. e.g.) [eax + eax*1] and [eax*2] must be distinguished and encoded differently. So a new EA flag EAF_MIB for mib operands is added. And a new EA hint EAH_SUMMED for the case of [eax+eax*4] being parsed as [eax*5] is also added. NOSPLIT specifier does not have an effect in mib, so [nosplit eax + eax*1] will be encoded as [eax, eax] rather than [eax*2] as in a regular EA. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-12-04bnd: Add a new nobnd prefixJin Kyu Song1-2/+25
bnd and nobnd prifixes can be used for each instruction line to direct whether bnd registers should be preserved or not. And those are also added as options for DEFAULT directive. Once bnd is set with default, DEFAULT BND, all bnd-prefix available instructions are prefixed with bnd. To override it, nobnd prefix can be used. In the other way, DEFAULT NOBND can disable DEFAULT BND and have nasm encode in the normal way. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-12-04bnd: Show warning when bnd prefix is droppedJin Kyu Song1-0/+2
When bnd prefix is dropped as jmp is encoded as jmp short, nasm shows a warning message, which can be suppressed with a new command line option, -w-bnd. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-28Add {vex3} and {vex2} prefixes by analogy with {evex}H. Peter Anvin1-6/+34
Allow specifying {vex3} or {vex2} (the latter is currently always redundant, unless we end up with instructions at some point can be specified with legacy prefixes or VEX) to select a specific encoding of VEX-encoded instructions. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-11-27iflags: Add IF_EVEX for checking {evex} availabilityJin Kyu Song1-3/+10
For checking the availability of {evex} prefix, AVX512 iflag has been used. But this is a flag for an instruction set not for an encoding scheme. And there are some AVX512 instructions encoded with VEX prefix. So a new instruction flag (IF_EVEX) is added for the instructions which are actually encoded with EVEX prefix. This flag is automatically added by insns.pl, so no need to add manually in insns.dat. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-27opflags: Separate vector registers into low-16 and high-16Jin Kyu Song1-4/+0
Since only EVEX supports all 32 vector registers encoding for now, VEX/REX encoded instructions should not take high-16 registers as operands. This filtering had been done using instruction flag so far, but using the opflags makes more sense. [XYZ]MMREG operands used for non-EVEX instructions are automatically converted to [XYZ]MM_L16 in insns.pl Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-24iflag: Start using new instruction flags engineCyrill Gorcunov1-28/+27
Here we start using instruction flags generator. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-11-22bnd: Drop bnd prefix for relaxed short jmp instructionsJin Kyu Song1-1/+12
Reverted the redundant branch instruction patterns for bnd prefix. And when a relaxed jmp instruction becomes a short (Jb) form, bnd prefix is not needed because it does not initialize bnd registers. So in that case, bnd prefix is silently dropped. BND JMP foo -> drops bnd prefix BND JMP short foo -> shows an explicit error Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20disp8: Consolidate a logic to get compressed displacementJin Kyu Song1-83/+2
Consolidated two separate but similar functions in nasm and ndisasm into a commonly linked source code. To encode and decode the compressed displacement (disp8*N) for EVEX, N value should be derived using various conditions. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20match: Check the number of elements in broadcasting operandsJin Kyu Song1-1/+20
The broadcasting decorator {1to##} must describe exactly how many times the memory element is repeated in order to clearly match the correct instruction format. For example, vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to8} ; good vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to16} ; fail qword * 16 = 1024b vaddps zmm30,zmm29,DWORD [rcx]{1to16} ; good vaddps zmm30,zmm29,DWORD [rcx]{1to8} ; fail dword * 8 = 256b Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20match: Improve broadcast opsize matchingJin Kyu Song1-20/+35
Broadcasting operand size is different from the original operand size because 32b or 64b element is repeated to form a vector. So when matching a broadcasting operand, opsize should be treated differently. The broadcasting element size is specified in the decorator information. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20AVX-512: Add {evex} instruction prefixJin Kyu Song1-0/+7
For instructions that can be encoded either in VEX or EVEX, {evex} forces nasm to encode in EVEX. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Move BND prefix indication from bytecode to iflagsJin Kyu Song1-3/+3
As BND prefix validity check conflicts with jcc8 prefix, IF_BND is added for the instruction templates which can have bnd prefix for preserving the content of bound register. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Adapt GAS's mib syntax with an index reg onlyJin Kyu Song1-0/+12
GAS uses *1 multiplier for explicitly marking an index register in mib operand. e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format So only for mib operands, this is encoded same as gas does. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Add BND prefix for branch instructionsJin Kyu Song1-2/+11
BND prefix is used for adding bounds checking protection across flow control changes such as call, ret, jmp and jcc calls. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Add MPX instructionsJin Kyu Song1-1/+22
Added MPX instructions and corresponding parser and encoder. ICC style mib - base + disp and index are separate - is supported. E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index As a supplement to NASM style mib - split EA - parser, omitted base+disp is now treated as 0 displacement. E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-08Add (redundant) parentheses around bit tests mixed with &&H. Peter Anvin1-3/+3
It is easy to get confused when mixing & and &&, so add redundant parenteses for clarity. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-11-08REX: Set REX bits in accordance with 32-register environmentJin Kyu Song1-7/+7
REX.RXB bits were set for high-8 registers previously. Since high-16 zmm registers are newly added, those bits should be set as one bit of binary number of register value. Similarly EVEX.R'/V'/X should be set in the same manner. Authored-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-09-21AVX-512: Fix bugs related to uninitialized variablesJin Kyu Song1-1/+3
Initialized disp8 to avoid a case that disp8 encoded instead of the actual offset value. Added a checking routine for basereg value before using it as an index of array. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-09-14AVX-512: Add AVX-512ER instructionsJin Kyu Song1-1/+1
Added Exponential and Reciprocal (AVX-512ER) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512ER[bit 27] = 1. IF_AVX512 is now shared by all AVX-512* instructions as a bit mask. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-09-07AVX-512: Fix rounding mode value in EVEX prefix with SAEJin Kyu Song1-6/+9
If SAE is set, VL(vector length) is implied to be 512. EVEX.L'L (=EVEX.RC) is set to 00b by default. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-29AVX-512: Fix bug in checking high-16 registersJin Kyu Song1-1/+1
Register value needs to be checked. Previous patch compared with reg_enum. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-29AVX-512: Remember the position of operand with broadcast or embedded roundingJin Kyu Song1-16/+8
It was not so straight forward to find the postion of operand that has a broadcasting, embedded rounding mode or SAE (Suppress All Exceptions) decorator out from operands types or bytecode. Remebering the postion of the operand of interest in the parser reduces the burden that assembler looks through the operands. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-28AVX-512: Fix match function to check the range of registersJin Kyu Song1-0/+8
High-16 registers of XMM and YMM need to be encoded with EVEX not VEX. Even if all the operand types match with VEX instruction format, it should use EVEX instead. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-28AVX-512: Change the data type for instruction flagsJin Kyu Song1-3/+3
Increased the size of data type for instruction flags from 32bits to 64bits. And a new type (iflags_t) is defined for better maintainability. Bigger data type is needed because more instruction set types are coming but there were not enough space for them. Since they are not bit masks, only one instruction set is allowed for each instruction. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-28AVX-512: Fix a bug in calculating Disp8*N valueJin Kyu Song1-1/+1
Fixed a bug that derived an incorrect N value for tuple types of T2, T4, T8. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-28AVX-512: Find the correct position of the last SIMD opJin Kyu Song1-0/+2
Since embedded rounding mode is following the last SIMD op, GPR op should be skipped when finding the last SIMD op. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-22AVX-512: Add ZWORD keywordJin Kyu Song1-0/+2
ZWORD (512 bits) keyword is added Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-22AVX-512: Fix instruction match functionJin Kyu Song1-4/+31
When an instruction allows broadcasting, the memory element size is different from the size of normal memory operation. This information is provided in a decoflags field, so it should try to match those properties before it fails. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-16AVX-512: Add EVEX encoding and new instructionsJin Kyu Song1-41/+285
EVEX encoding support includes 32 vector regs (XMM/YMM/ZMM), opmask, broadcasting, embedded rounding mode, suppress all exceptions, compressed displacement. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-04-01Fixed several resource and memory leaksPhilipp Kloke1-0/+1
Bug found by: CppCheck 1.59 (static source analysis tool) Signed-off-by: Philipp Kloke <philipp.kloke@web.de> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-10Make F2 and F3 SSE prefixes override 66Ben Rudiak-Gould1-10/+1
According to XED and experimentation, the 66 is ignored. Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-04Drop SAME_AS flag from instruction matcherBen Rudiak-Gould1-17/+4
It was there to support the SSE5 DREX encoding, which as far as I know is dead forever. Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-03insns: Remove pushseg/popseg internal bytecodesBen Rudiak-Gould1-50/+0
This patch is getting rid of the following bytecodes 'pushseg','popseg','pushseg2','popseg2' and simplifies overall code. [gorcunov@: a few style fixes] Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-03Move conditional opcodes close to enum ccode definitionCyrill Gorcunov1-6/+1
Thus if someone need to rework this code he won't need to jump between files trying to figure out where enum and opcodes lay. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-02assemble: Make emit_rex being a functionCyrill Gorcunov1-8/+14
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-02assemble: Use case3/4 where appropriateCyrill Gorcunov1-16/+5
This allows to shrink code a bit. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-02assemble: Add case3 helperCyrill Gorcunov1-1/+2
Signed-off-by: cyrill <cyrill@cyrills-MacBook-Pro.local>
2013-03-02process_ea: Drop redundant variableCyrill Gorcunov1-5/+1
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-01Remove +sBen Rudiak-Gould1-181/+29
It doesn't seem worth >200 lines of C and Perl to save ~50 lines in insns.dat. In order to make this work I had to rename sbyte16/sbyte32 so that they can take an ordinary size suffix (their size suffix was formerly treated specially). This fixes one disassembly bug: 48C7C000000080 disassembles to mov rax,0x80000000, which reassembles to B800000080, which loads a different value. Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Acked-by: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-02-20Add np and similar prefixes to instructions that should have themBen Rudiak-Gould1-0/+8
This adds "np" to a bunch of SSE-style instructions that should have it, "norep" (which was implemented but unused) on quasi-SSE instructions that use F2 and F3 as instruction extensions but 66 for operand size, "nof3" (newly implemented) on a few instructions, "norexw" on some instructions that have only 32-bit and 64-bit versions, and one NOLONG. It also removes some incorrect "np"s, changes some "f3"s to "f3i"s, and fixes the decoding of the XCHG/NOP/PAUSE mess: F390 is always PAUSE even when rex.b=1 (at least according to XED). Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2012-09-10opflags: Extend opflags_t to 64 bitsCyrill Gorcunov1-3/+4
Soon we will need to encode 512 bits values thus there is no space left in our opflags_t which is 32 bitfield. Extend it to 64 bits width. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2012-02-25HLE: One more byte code conversionH. Peter Anvin1-3/+3
Add missing site for the \265..267 -> \271..273 byte code move. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-25HLE: Move byte codes back to \271-\273H. Peter Anvin1-10/+9
Since we are back to three bytecodes, move them back to the \271-\273 slot to free up the \264 complete quad. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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