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2013-11-28Add {vex3} and {vex2} prefixes by analogy with {evex}H. Peter Anvin8-13/+62
Allow specifying {vex3} or {vex2} (the latter is currently always redundant, unless we end up with instructions at some point can be specified with legacy prefixes or VEX) to select a specific encoding of VEX-encoded instructions. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-11-28NASM 2.11rc2H. Peter Anvin1-1/+1
2013-11-28Remove "high 16" register class macros for xmm/ymm/zmmH. Peter Anvin2-12/+6
The "high 16" register class macros were actually incorrect, as they simply aliased the corresponding whole set class. In oder to keep someone from getting confused and making mistakes, remove them. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-27testcase: Remove escape characters - '\'Jin Kyu Song5-4401/+4401
Since the multi-line macro preprocessor is modified to expand grouped parameter with braces. The escape character is not needed any more. The testcase converter script is also modified not to generate '\'. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-27preproc: Handle curly braces in multi-line macro parametersJin Kyu Song1-13/+29
Multi-line macro uses curly braces for enclosing a parameter containing comma(s). Passing curly braces as a part of a parameter which is already enclosed with braces confuses the macro expander. The number of braces in a group parameter is counted and any brace in the outmost enclosing braces is treated as a part of parameter. e.g.) mmacro {1,2,3}, {4,{5,6}} mmacro gets 2 parameters of '1,2,3' and '4,{5,6}' Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-27Revert "AVX-512: Handle curly braces in multi-line macro parameters"Jin Kyu Song1-5/+0
This reverts commit a800aed7b75d56114f2e1e4928cbc48ecf96a4a0. As recommended by the community, braces inside a group parameter of multi-line macro should be parsed without a need of a leading escape character such as "\{ab,c\}". Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-27stdscan: Rework curly brace parsing routinesJin Kyu Song4-65/+54
As recommended by the community, a comma-separated decorators ({k1,z}) and nested braces ({{k1},{z}}) are dropped out. So only standard syntax is supported from now. This rework made source code neat and easy to maintain. Most of the codes for handling corner cases are removed. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-27iflags: Add IF_EVEX for checking {evex} availabilityJin Kyu Song3-6/+12
For checking the availability of {evex} prefix, AVX512 iflag has been used. But this is a flag for an instruction set not for an encoding scheme. And there are some AVX512 instructions encoded with VEX prefix. So a new instruction flag (IF_EVEX) is added for the instructions which are actually encoded with EVEX prefix. This flag is automatically added by insns.pl, so no need to add manually in insns.dat. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-27opflags: Separate vector registers into low-16 and high-16Jin Kyu Song4-11/+34
Since only EVEX supports all 32 vector registers encoding for now, VEX/REX encoded instructions should not take high-16 registers as operands. This filtering had been done using instruction flag so far, but using the opflags makes more sense. [XYZ]MMREG operands used for non-EVEX instructions are automatically converted to [XYZ]MM_L16 in insns.pl Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-27doc: Update the change history and nasmdocJin Kyu Song2-3/+84
Added the list of features added since 2.10 release. Nasmdoc is also updated with those new features. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-27disasm: Don't rely on iflag_cmp() returning +/-1H. Peter Anvin1-1/+2
It is safer to just rely on the sign, for future options. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-11-27iflag: Do the equality test in iflag_cmp() firstH. Peter Anvin1-4/+4
The equality test indicates how long we spin, so do that first. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-11-26iflag: In iflag_cmp() scan from the most significant word downH. Peter Anvin2-4/+7
In order for iflag_cmp() to return an ordering that makes sense, we need to scan from the most significant word downward. That way the bits with the higher index consistently are the more significant. This fixes the disassembler vendor selection algorithm. While we are doing that, make that dependency more explicit in the comments. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-24iflag: Drop the use of double underscoresH. Peter Anvin1-9/+9
Double underscores are reserved for the implementation, i.e. the C compiler and its libraries. NASM is an application and should not use this namespace. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-24iflag: Make the insns_flags array constH. Peter Anvin2-9/+11
Make the insns_flags array const, and change the helper functions to match. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-24insns.dat: Fix a typo in a commentH. Peter Anvin1-1/+1
isnsn-iflags.pl not insns-iflag.pl. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-24iflag: Move instruction flag commentH. Peter Anvin3-35/+29
Move the instruction flag comment to the Perl file where they are defined. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-24iflag: remove C99 constructs, don't hardcode the number of wordsH. Peter Anvin2-30/+27
Avoid using C99 constructs when not necessary. Don't hardcode the number of words when we can autodiscover them. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-24"make alldeps"H. Peter Anvin5-133/+145
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-24iflag: Fix dependencies, factor out static components of iflag.hH. Peter Anvin5-216/+223
Multi-dependencies don't work as expected, especially not across Make versions, this is why we don't use them and read the instructions list multiple times. iflag.h has a lot of static content, so factor out the static content. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-24"make alldeps"H. Peter Anvin5-30/+48
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2013-11-24insns: Restore back MMX,FPU flagsCyrill Gorcunov2-38/+23
In commit 9bb987d8e0330429afba42015b1fc7c7ca0d1b16 we had to drop some flags due to flags type used in nasm code. Since now flags internal structure is reworked, we can restore them back. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-11-24Update .gitignoreCyrill Gorcunov1-0/+2
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-11-24make: Update depsCyrill Gorcunov5-126/+146
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-11-24iflag: Start using new instruction flags engineCyrill Gorcunov13-234/+182
Here we start using instruction flags generator. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-11-24insns: Introduce insns-flags.plCyrill Gorcunov1-0/+410
It been found that 64 bits for instruction flags is too small, so instead we start using indirect addressing scheme to keep instruction flags in bitvectors instead. Using one bitvector per instruction template entry is wastefull (especially if vector grow in future, at moment it's 128 bit length), so we use indirect addressing, which is generated as follow - read instruction flags from insns.dat - flag sequence sorted and joined into one key string - this key string become a hash index - all hash entries are compacted into one array - every instruction template uses array offset instead of flags bitfield Just for info, at moment we have 195 unique flags combination, but since instruction template will use index as unsigned integer, we can use a way more wider combination of flags in future. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-11-24make: Add 'golden' targetCyrill Gorcunov1-0/+3
We've 'test' target in toplevel Makefile, lets be complete and allow to generate "golden" tests from toplevel as well. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-11-22bnd: Drop bnd prefix for relaxed short jmp instructionsJin Kyu Song4-97/+65
Reverted the redundant branch instruction patterns for bnd prefix. And when a relaxed jmp instruction becomes a short (Jb) form, bnd prefix is not needed because it does not initialize bnd registers. So in that case, bnd prefix is silently dropped. BND JMP foo -> drops bnd prefix BND JMP short foo -> shows an explicit error Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20disp8: Consolidate a logic to get compressed displacementJin Kyu Song5-155/+181
Consolidated two separate but similar functions in nasm and ndisasm into a commonly linked source code. To encode and decode the compressed displacement (disp8*N) for EVEX, N value should be derived using various conditions. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20disasm: Add suport for bnd registersJin Kyu Song1-0/+7
MPX uses a new bnd registers and a new mib syntax. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20disasm: Add EVEX decorator syntaxJin Kyu Song1-9/+92
Broadcasting, opmask, embedded rounding and SAE decorators are not added at proper position. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20disasm: Add ZMM vsibJin Kyu Song1-4/+12
ZMM registers can be used for vsib index and the number of registers has been increased to 32. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20disasm: Support EVEX compressed displacementJin Kyu Song1-11/+107
When tuple type is indicated in the bytecode, disp8 is treated as a compressed disp and gets calculated back to disp8*N. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20disasm: Add basic AVX512 supportJin Kyu Song3-6/+100
Disassembler can translate EVEX prefix, count up to 32 vector registers and recognize new ZMM / opmask registers. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20disasm: style cleanupJin Kyu Song1-682/+682
Fix indentation. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20match: Check the number of elements in broadcasting operandsJin Kyu Song3-2/+36
The broadcasting decorator {1to##} must describe exactly how many times the memory element is repeated in order to clearly match the correct instruction format. For example, vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to8} ; good vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to16} ; fail qword * 16 = 1024b vaddps zmm30,zmm29,DWORD [rcx]{1to16} ; good vaddps zmm30,zmm29,DWORD [rcx]{1to8} ; fail dword * 8 = 256b Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20match: Improve broadcast opsize matchingJin Kyu Song1-20/+35
Broadcasting operand size is different from the original operand size because 32b or 64b element is repeated to form a vector. So when matching a broadcasting operand, opsize should be treated differently. The broadcasting element size is specified in the decorator information. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20Build: Suppress warning messagesJin Kyu Song2-2/+2
Giving a correct printf format specifier supresses the warning message. And a local pointer variable is initialized with NULL. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20AVX-512: Add {evex} instruction prefixJin Kyu Song4-0/+14
For instructions that can be encoded either in VEX or EVEX, {evex} forces nasm to encode in EVEX. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20PREFETCHWT1: Add a new instruction flagJin Kyu Song2-1/+2
PREFETCHWT1 instruction's CPUID was TBD before. Now it has its new CPUID bit : PREFETCHWT1 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20AVX512: Update instruction groupJin Kyu Song1-2/+2
CPUID bit for vptestnm[dq] changed. vptestnm[dq]: AVX512CD -> AVX512F Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Move BND prefix indication from bytecode to iflagsJin Kyu Song5-56/+50
As BND prefix validity check conflicts with jcc8 prefix, IF_BND is added for the instruction templates which can have bnd prefix for preserving the content of bound register. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Adapt GAS's mib syntax with an index reg onlyJin Kyu Song2-4/+16
GAS uses *1 multiplier for explicitly marking an index register in mib operand. e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format So only for mib operands, this is encoded same as gas does. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20iflags: Use UINT64_C() for 64bit valuesJin Kyu Song1-79/+79
UINT64_C() macro is used for iflags as it becomes 64bit. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20SHA: SHA test casesJin Kyu Song2-0/+61
32bit and 64bit test asm files. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20SHA: Add SHA instructionsJin Kyu Song2-0/+10
New instruction extensions of SHA family are added. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Add test cases for MPXJin Kyu Song2-0/+202
MPX test asm files are added. These include all three different styles of mib syntax (NASM, ICC and gas). Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Add BND prefix for branch instructionsJin Kyu Song8-3/+75
BND prefix is used for adding bounds checking protection across flow control changes such as call, ret, jmp and jcc calls. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Add MPX instructionsJin Kyu Song7-2/+61
Added MPX instructions and corresponding parser and encoder. ICC style mib - base + disp and index are separate - is supported. E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index As a supplement to NASM style mib - split EA - parser, omitted base+disp is now treated as 0 displacement. E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20disasm: add support for emitting split EA formatH. Peter Anvin2-2/+16
Add support for emitting split EA format in the disassembler, indicated by the MIB instruction flag. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
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