diff options
| -rw-r--r-- | doc/changes.src | 57 | ||||
| -rw-r--r-- | doc/nasmdoc.src | 30 |
2 files changed, 84 insertions, 3 deletions
diff --git a/doc/changes.src b/doc/changes.src index bcd2ee6..91e3078 100644 --- a/doc/changes.src +++ b/doc/changes.src @@ -7,6 +7,63 @@ The NASM 2 series supports x86-64, and is the production version of NASM since 2007. +\S{cl-2.11} Version 2.11 + +\b Instruction flags use bitvectors as 64-bit bitfields were doomed +to be cramped soon. All possible bitvectors are sorted and hashed. So +each unique bitvector occupies only one hash index. + +\b Add support for \c{DZ} and \c{RESZ} + +\b Better handling of section redefinition + +\b Generate manpages when running \c{'make dist'} + +\b Handle all token chains in mmacro params range + +\b Support split [base,index] effective address + +\c mov eax,[eax+8,ecx*4] ; eax=base, ecx=index, 4=scale, 8=disp + +\b Add support for MPX/SHA instructions + +\b Support \c{BND} prefix for branch instructions + +\b Add \c{{evex}} instruction prefix to have nasm encode the corresponding +instruction line with EVEX + +\b Ndisasm supports AVX-512/MPX/SHA instructions + +\S{cl-2.11rc1} Version 2.11rc1 + +\b Support for Intel AVX-512 instruction set. The document introducing these +instrustions can be found at +\W{http://download-software.intel.com/sites/default/files/319433-016.pdf}{intel.com} +. Added features are as follows : + +\b 16 new, 512-bit SIMD registers. Total 32 \c{(ZMM0 ~ ZMM31)} + +\b 8 new opmask registers \c{(K0 ~ K7)}. One of 7 registers \c{(K1 ~ K7)} can +be used as an opmask for conditional execution. + +\b A new EVEX encoding prefix. EVEX is based on VEX and provides more +capabilities: opmasks, broadcasting, embedded rounding and compressed +displacements. + +\c - opmask +\c VDIVPD zmm0{k1}{z}, zmm1, zmm3 ; conditional vector operation +\c ; using opmask k1. +\c ; {z} is for zero-masking +\c - broadcasting +\c VDIVPS zmm4, zmm5, [rbx]{1to16} ; load single-precision float and +\c ; replicate it 16 times. 32 * 16 = 512 +\c - embedded rounding +\c VCVTSI2SD xmm6, xmm7, {rz-sae}, rax ; round toward zero. note that it +\c ; is used as if a separate operand. +\c ; it comes after the last SIMD operand + +\b Support for section names longer than 8 bytes + \S{cl-2.10.09} Version 2.10.09 \b Pregenerate man pages. diff --git a/doc/nasmdoc.src b/doc/nasmdoc.src index bfd7593..2ba24c2 100644 --- a/doc/nasmdoc.src +++ b/doc/nasmdoc.src @@ -1213,9 +1213,9 @@ an identifier is 4095 characters. The instruction field may contain any machine instruction: Pentium and P6 instructions, FPU instructions, MMX instructions and even undocumented instructions are all supported. The instruction may be -prefixed by \c{LOCK}, \c{REP}, \c{REPE}/\c{REPZ} or -\c{REPNE}/\c{REPNZ}, in the usual way. Explicit \I{address-size -prefixes}address-size and \i{operand-size prefixes} \i\c{A16}, +prefixed by \c{LOCK}, \c{REP}, \c{REPE}/\c{REPZ}, \c{REPNE}/\c{REPNZ}, +\c{XACQUIRE}/\c{XRELEASE} or \c{BND}, in the usual way. Explicit +\I{address-size prefixes}address-size and \i{operand-size prefixes} \i\c{A16}, \i\c{A32}, \i\c{A64}, \i\c{O16} and \i\c{O32}, \i\c{O64} are provided - one example of their use is given in \k{mixsize}. You can also use the name of a \I{segment override}segment register as an instruction prefix: coding @@ -1462,6 +1462,30 @@ In 64-bit mode, NASM will by default generate absolute addresses. The this is frequently the normally desired behaviour, see the \c{DEFAULT} directive (\k{default}). The keyword \i\c{ABS} overrides \i\c{REL}. +A new form of split effective addres syntax is also supported. This is mainly +intended for mib operand but can be used for any memory reference. The basic +concept of this form is splitting base and index. + +\c mov eax,[ebx+8,ecx*4] ; ebx=base, ecx=index, 4=scale, 8=disp + +For mib operands, there are several ways of writing effective address depending +on the tools. NASM supports all currently possible ways of mib syntax: + +\c ; bndstx +\c ; next 5 lines are parsed same +\c ; base=rax, index=rbx, scale=1, displacement=3 +\c bndstx [rax+0x3,rbx], bnd0 ; NASM - split EA +\c bndstx [rbx*1+rax+0x3], bnd0 ; GAS - '*1' indecates an index reg +\c bndstx [rax+rbx+3], bnd0 ; GAS - without hints +\c bndstx [rax+0x3], bnd0, rbx ; ICC-1 +\c bndstx [rax+0x3], rbx, bnd0 ; ICC-2 + +When broadcasting decorator is used, the opsize keyword should match +the size of each element. + +\c VDIVPS zmm4, zmm5, dword [rbx]{1to16} ; single-precision float +\c VDIVPS zmm4, zmm5, zword [rbx] ; packed 512 bit memory + \H{const} \i{Constants} |