diff options
author | H. Peter Anvin <hpa@zytor.com> | 2007-11-12 20:18:05 -0800 |
---|---|---|
committer | H. Peter Anvin <hpa@zytor.com> | 2007-11-12 20:18:05 -0800 |
commit | aff9c93aa462f8822341c5207a55dd92a7aead2e (patch) | |
tree | 24710a5f4ded9989241bc8d65f8614d6c5d38994 /regs.dat | |
parent | ce6c8a7929dff3ab47a1a9481591e0eefcb562a9 (diff) | |
download | nasm-aff9c93aa462f8822341c5207a55dd92a7aead2e.tar.gz nasm-aff9c93aa462f8822341c5207a55dd92a7aead2e.tar.bz2 nasm-aff9c93aa462f8822341c5207a55dd92a7aead2e.zip |
Fix handling of XCHG in 64-bit mode
The handling of XCHG in 64-bit mode somewhat broken. Add a register
flag for "not accumulator", so we can generate all the appropriate
modes.
Diffstat (limited to 'regs.dat')
-rw-r--r-- | regs.dat | 48 |
1 files changed, 24 insertions, 24 deletions
@@ -16,11 +16,11 @@ ah REG_HIGH reg8 4 ax REG_AX reg16 0 eax REG_EAX reg32 0 rax REG_RAX reg64 0 -bl REG8 reg8,reg8_rex 3 +bl REG8NA reg8,reg8_rex 3 bh REG_HIGH reg8 7 -bx REG16 reg16 3 -ebx REG32 reg32 3 -rbx REG64 reg64 3 +bx REG16NA reg16 3 +ebx REG32NA reg32 3 +rbx REG64NA reg64 3 cl REG_CL reg8,reg8_rex 1 ch REG_HIGH reg8 5 cx REG_CX reg16 1 @@ -31,26 +31,26 @@ dh REG_HIGH reg8 6 dx REG_DX reg16 2 edx REG_EDX reg32 2 rdx REG_RDX reg64 2 -spl REG8 reg8_rex 4 -sp REG16 reg16 4 -esp REG32 reg32 4 -rsp REG64 reg64 4 -bpl REG8 reg8_rex 5 -bp REG16 reg16 5 -ebp REG32 reg32 5 -rbp REG64 reg64 5 -sil REG8 reg8_rex 6 -si REG16 reg16 6 -esi REG32 reg32 6 -rsi REG64 reg64 6 -dil REG8 reg8_rex 7 -di REG16 reg16 7 -edi REG32 reg32 7 -rdi REG64 reg64 7 -r8-15b REG8 reg8_rex 8 -r8-15w REG16 reg16 8 -r8-15d REG32 reg32 8 -r8-15 REG64 reg64 8 +spl REG8NA reg8_rex 4 +sp REG16NA reg16 4 +esp REG32NA reg32 4 +rsp REG64NA reg64 4 +bpl REG8NA reg8_rex 5 +bp REG16NA reg16 5 +ebp REG32NA reg32 5 +rbp REG64NA reg64 5 +sil REG8NA reg8_rex 6 +si REG16NA reg16 6 +esi REG32NA reg32 6 +rsi REG64NA reg64 6 +dil REG8NA reg8_rex 7 +di REG16NA reg16 7 +edi REG32NA reg32 7 +rdi REG64NA reg64 7 +r8-15b REG8NA reg8_rex 8 +r8-15w REG16NA reg16 8 +r8-15d REG32NA reg32 8 +r8-15 REG64NA reg64 8 # Segment registers cs REG_CS sreg 1 |