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author | Cyrill Gorcunov <gorcunov@gmail.com> | 2013-10-27 01:20:42 +0400 |
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committer | Cyrill Gorcunov <gorcunov@gmail.com> | 2013-11-24 13:20:52 +0400 |
commit | d4e51d3e718a6bcf19151ed90caec1754ea94dec (patch) | |
tree | 4ee3b20e996ccd643bf691343f3c479b81316fb4 /nasm.c | |
parent | acfb97d3db0b91742465540c4558890e3c80fc8a (diff) | |
download | nasm-d4e51d3e718a6bcf19151ed90caec1754ea94dec.tar.gz nasm-d4e51d3e718a6bcf19151ed90caec1754ea94dec.tar.bz2 nasm-d4e51d3e718a6bcf19151ed90caec1754ea94dec.zip |
insns: Introduce insns-flags.pl
It been found that 64 bits for instruction flags is too small,
so instead we start using indirect addressing scheme to keep
instruction flags in bitvectors instead.
Using one bitvector per instruction template entry is wastefull
(especially if vector grow in future, at moment it's 128 bit length),
so we use indirect addressing, which is generated as follow
- read instruction flags from insns.dat
- flag sequence sorted and joined into one key string
- this key string become a hash index
- all hash entries are compacted into one array
- every instruction template uses array offset instead
of flags bitfield
Just for info, at moment we have 195 unique flags combination,
but since instruction template will use index as unsigned
integer, we can use a way more wider combination of flags
in future.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Diffstat (limited to 'nasm.c')
0 files changed, 0 insertions, 0 deletions