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| author | H. Peter Anvin <hpa@zytor.com> | 2007-09-19 21:41:27 -0700 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2007-09-19 21:41:27 -0700 |
| commit | d9a979559e76028f671891483134251656793d0c (patch) | |
| tree | 9e0201304bf232a1c2afb3e67b9aa375c22b7870 /nasm.1 | |
| parent | 8d024e7965efb208b0831ee7289329f85cf4433f (diff) | |
| download | nasm-d9a979559e76028f671891483134251656793d0c.tar.gz nasm-d9a979559e76028f671891483134251656793d0c.tar.bz2 nasm-d9a979559e76028f671891483134251656793d0c.zip | |
Update manual pages
Update manual pages to include 64-bit support, and remove section
about sync point limits in ndisasm.
Diffstat (limited to 'nasm.1')
| -rw-r--r-- | nasm.1 | 10 |
1 files changed, 6 insertions, 4 deletions
@@ -192,9 +192,10 @@ is reserved using the .IR RESB , .IR RESW , .IR RESD , -.I RESQ -and +.IR RESQ , .I REST +and +.I RESO pseudo-opcodes, each taking one parameter which gives the number of bytes, words, doublewords, quadwords or ten-byte words to reserve. .PP @@ -297,9 +298,10 @@ finished doing absolute assembly, you must issue another .I SECTION directive to return to normal assembly. .PP -.I BITS 16 -or +.I BITS 16, .I BITS 32 +or +.I BITS 64 switches the default processor mode for which .B nasm is generating code: it is equivalent to |