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author | H. Peter Anvin <hpa@zytor.com> | 2007-09-17 17:25:27 -0700 |
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committer | H. Peter Anvin <hpa@zytor.com> | 2007-09-17 17:25:27 -0700 |
commit | cf5180a9553e43bbaa46fd1a77c75dc8b7f6da42 (patch) | |
tree | e49a78cca72852670b210bce53f4c5698fc4c7bf /insns.pl | |
parent | 401c07e20d14130a2d147468a408fce9edd1faff (diff) | |
download | nasm-cf5180a9553e43bbaa46fd1a77c75dc8b7f6da42.tar.gz nasm-cf5180a9553e43bbaa46fd1a77c75dc8b7f6da42.tar.bz2 nasm-cf5180a9553e43bbaa46fd1a77c75dc8b7f6da42.zip |
Actually generate SSE5 instructions
This checkin completes what is required to actually generate SSE5
instructions. No support in the disassembler yet.
This checkin covers:
- Support for actually generating DREX prefixes.
- Support for matching operand "operand X must match Y"
Diffstat (limited to 'insns.pl')
-rw-r--r-- | insns.pl | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -218,6 +218,7 @@ sub format { $operands =~ s/rm(\d+)/rm_gpr|bits$1/g; $operands =~ s/mmxrm/rm_mmx/g; $operands =~ s/xmmrm/rm_xmm/g; + $operands =~ s/\=([0-9]+)/same_as|$1/g; if ($operands eq 'void') { @ops = (); } else { |