opflags: Separate vector registers into low-16 and high-16

Since only EVEX supports all 32 vector registers encoding for now,
VEX/REX encoded instructions should not take high-16 registers as operands.

This filtering had been done using instruction flag so far, but
using the opflags makes more sense.

[XYZ]MMREG operands used for non-EVEX instructions are automatically
converted to [XYZ]MM_L16 in insns.pl

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/insns.pl b/insns.pl
index 8515c02..2ce9a51 100755
--- a/insns.pl
+++ b/insns.pl
@@ -464,6 +464,11 @@ sub format_insn($$$$$) {
                 $opp =~ s/^([a-z]+)rm$/rm_$1/;
                 $opp =~ s/^rm$/rm_gpr/;
                 $opp =~ s/^reg$/reg_gpr/;
+                # only for evex insns, high-16 regs are allowed
+                if ($codes !~ /(^|\s)evex\./) {
+                    $opp =~ s/^(rm_[xyz]mm)$/$1_l16/;
+                    $opp =~ s/^([xyz]mm)reg$/$1_l16/;
+                }
                 push(@opx, $opp, @oppx) if $opp;
             }
             $op = join('|', @opx);