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author | H. Peter Anvin <hpa@zytor.com> | 2008-05-23 17:46:08 -0700 |
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committer | H. Peter Anvin <hpa@zytor.com> | 2008-05-23 17:46:08 -0700 |
commit | dd84acedccfbd6ce1ed4371623779084ddfb0f48 (patch) | |
tree | 75ec815ddd31c33c4ffb089457232882ca59cc84 /insns.h | |
parent | 55ca614e62ec7c84f158e98976b4c21a4c00600f (diff) | |
download | nasm-dd84acedccfbd6ce1ed4371623779084ddfb0f48.tar.gz nasm-dd84acedccfbd6ce1ed4371623779084ddfb0f48.tar.bz2 nasm-dd84acedccfbd6ce1ed4371623779084ddfb0f48.zip |
AVX FMA: Instruction table for the AVX FMA instructions
This adds the AVX FMA instructions to the instruction table, which
should complete the AVX work.
Diffstat (limited to 'insns.h')
-rw-r--r-- | insns.h | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -104,9 +104,10 @@ extern const uint8_t nasm_bytecodes[]; #define IF_SSE42 0x00800000UL /* HACK NEED TO REORGANIZE THESE BITS */ #define IF_SSE5 0x00800000UL /* HACK NEED TO REORGANIZE THESE BITS */ #define IF_AVX 0x00800000UL /* HACK NEED TO REORGANIZE THESE BITS */ +#define IF_FMA 0x00800000UL /* HACK NEED TO REORGANIZE THESE BITS */ #define IF_PMASK 0xFF000000UL /* the mask for processor types */ #define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */ - /* also the highest possible processor */ + /* also the highest possible processor */ #define IF_PFMASK 0xF01FFF00UL /* the mask for disassembly "prefer" */ #define IF_8086 0x00000000UL /* 8086 instruction */ #define IF_186 0x01000000UL /* 186+ instruction */ |