diff options
| author | Jin Kyu Song <jin.kyu.song@intel.com> | 2013-08-28 19:15:26 -0700 |
|---|---|---|
| committer | Cyrill Gorcunov <gorcunov@gmail.com> | 2013-08-29 10:03:19 +0400 |
| commit | b21f97db0e5dc785092ec168b0bacd4d1f6ddfce (patch) | |
| tree | e78a9292f792d2cdce1774a8c8c10b804219bc69 /insns.h | |
| parent | 7abc78dee0b88125d5fb3175568c62f6d0cfb9a8 (diff) | |
| download | nasm-b21f97db0e5dc785092ec168b0bacd4d1f6ddfce.tar.gz nasm-b21f97db0e5dc785092ec168b0bacd4d1f6ddfce.tar.bz2 nasm-b21f97db0e5dc785092ec168b0bacd4d1f6ddfce.zip | |
AVX-512: Add IF_SPMASK and fix IF_PFMASK
Defined IF_SPMASK for specific processor types and
fixed IF_PFMASK to mask the exact preferred bits only.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Diffstat (limited to 'insns.h')
| -rw-r--r-- | insns.h | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -132,7 +132,6 @@ extern const uint8_t nasm_bytecodes[]; #define IF_PMASK 0xFF000000UL /* the mask for processor types */ #define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */ /* also the highest possible processor */ -#define IF_PFMASK 0xFFF0000000UL /* the mask for disassembly "prefer" */ #define IF_8086 0x00000000UL /* 8086 instruction */ #define IF_186 0x01000000UL /* 186+ instruction */ #define IF_286 0x02000000UL /* 286+ instruction */ @@ -152,5 +151,7 @@ extern const uint8_t nasm_bytecodes[]; #define IF_IA64 0x0F000000UL /* IA64 instructions (in x86 mode) */ #define IF_CYRIX 0x10000000UL /* Cyrix-specific instruction */ #define IF_AMD 0x20000000UL /* AMD-specific instruction */ +#define IF_SPMASK 0x30000000UL /* specific processor types mask */ +#define IF_PFMASK (IF_INSMASK|IF_SPMASK) /* disassembly "prefer" mask */ #endif /* NASM_INSNS_H */ |