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| author | Jin Kyu Song <jin.kyu.song@intel.com> | 2013-10-15 19:10:13 -0700 |
|---|---|---|
| committer | Jin Kyu Song <jin.kyu.song@intel.com> | 2013-11-20 11:29:41 -0800 |
| commit | 164d60740f0aa2759ae78874bd5c8692d8d59e60 (patch) | |
| tree | 237161a1e4ac230347feefa20a9ed1fc0b80a27a /insns.h | |
| parent | 0bc288f8b9ec5fb30fb816008e81282081d85e82 (diff) | |
| download | nasm-164d60740f0aa2759ae78874bd5c8692d8d59e60.tar.gz nasm-164d60740f0aa2759ae78874bd5c8692d8d59e60.tar.bz2 nasm-164d60740f0aa2759ae78874bd5c8692d8d59e60.zip | |
MPX: Add MPX instructions
Added MPX instructions and corresponding parser and encoder.
ICC style mib - base + disp and index are separate - is supported.
E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index
As a supplement to NASM style mib - split EA - parser,
omitted base+disp is now treated as 0 displacement.
E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Diffstat (limited to 'insns.h')
| -rw-r--r-- | insns.h | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -132,6 +132,7 @@ extern const uint8_t nasm_bytecodes[]; #define IF_AVX512CD (0x1600000000UL|IF_AVX512) /* AVX-512 Conflict Detection insns */ #define IF_AVX512ER (0x1700000000UL|IF_AVX512) /* AVX-512 Exponential and Reciprocal */ #define IF_AVX512PF (0x1800000000UL|IF_AVX512) /* AVX-512 Prefetch instructions */ +#define IF_MPX 0x1900000000UL /* MPX instructions */ #define IF_INSMASK 0xFF00000000UL /* the mask for instruction set types */ #define IF_PMASK 0xFF000000UL /* the mask for processor types */ #define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */ |