diff options
| author | Jin Kyu Song <jin.kyu.song@intel.com> | 2013-08-15 19:01:25 -0700 |
|---|---|---|
| committer | Cyrill Gorcunov <gorcunov@gmail.com> | 2013-08-16 09:06:15 +0400 |
| commit | cc1dc9de53137e864bde06573556723149239f29 (patch) | |
| tree | ba84247ccd27964e56e29384b05a4ab1da169d9c /insns.h | |
| parent | 72018a2b4326d5a647b8879ba8124300b68ca212 (diff) | |
| download | nasm-cc1dc9de53137e864bde06573556723149239f29.tar.gz nasm-cc1dc9de53137e864bde06573556723149239f29.tar.bz2 nasm-cc1dc9de53137e864bde06573556723149239f29.zip | |
AVX-512: Add EVEX encoding and new instructions
EVEX encoding support includes 32 vector regs (XMM/YMM/ZMM),
opmask, broadcasting, embedded rounding mode,
suppress all exceptions, compressed displacement.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Diffstat (limited to 'insns.h')
| -rw-r--r-- | insns.h | 10 |
1 files changed, 7 insertions, 3 deletions
@@ -12,10 +12,12 @@ #include "nasm.h" #include "tokens.h" +/* if changed, ITEMPLATE_END should be also changed accordingly */ struct itemplate { enum opcode opcode; /* the token, passed from "parser.c" */ int operands; /* number of operands */ opflags_t opd[MAX_OPERANDS]; /* bit flags for operand types */ + decoflags_t deco[MAX_OPERANDS]; /* bit flags for operand decorators */ const uint8_t *code; /* the code it assembles to */ uint32_t flags; /* some flags */ }; @@ -35,7 +37,7 @@ struct disasm_index { /* Tables for the assembler and disassembler, respectively */ extern const struct itemplate * const nasm_instructions[]; extern const struct disasm_index itable[256]; -extern const struct disasm_index * const itable_vex[2][32][4]; +extern const struct disasm_index * const itable_vex[NASM_VEX_CLASSES][32][4]; /* Common table for the byte codes */ extern const uint8_t nasm_bytecodes[]; @@ -43,7 +45,7 @@ extern const uint8_t nasm_bytecodes[]; /* * this define is used to signify the end of an itemplate */ -#define ITEMPLATE_END {-1,-1,{-1,-1,-1},NULL,0} +#define ITEMPLATE_END {-1,-1,{-1,-1,-1,-1,-1},{-1,-1,-1,-1,-1},NULL,0} /* * Instruction template flags. These specify which processor @@ -80,7 +82,8 @@ extern const uint8_t nasm_bytecodes[]; #define IF_SQ 0x00000010UL /* unsized operands can't be non-qword */ #define IF_SO 0x00000014UL /* unsized operands can't be non-oword */ #define IF_SY 0x00000018UL /* unsized operands can't be non-yword */ -#define IF_SZ 0x00000038UL /* unsized operands must match the bitsize */ +#define IF_SZ 0x0000001CUL /* unsized operands can't be non-zword */ +#define IF_SIZE 0x00000038UL /* unsized operands must match the bitsize */ #define IF_SX 0x0000003CUL /* unsized operands not allowed */ #define IF_SMASK 0x0000003CUL /* mask for unsized argument size */ #define IF_AR0 0x00000040UL /* SB, SW, SD applies to argument 0 */ @@ -115,6 +118,7 @@ extern const uint8_t nasm_bytecodes[]; #define IF_SSE5 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */ #define IF_AVX 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */ #define IF_AVX2 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */ +#define IF_AVX512 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */ #define IF_FMA 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */ #define IF_BMI1 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */ #define IF_BMI2 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */ |