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authorH. Peter Anvin <hpa@zytor.com>2003-02-24 23:22:45 +0000
committerH. Peter Anvin <hpa@zytor.com>2003-02-24 23:22:45 +0000
commit10101f26bc4a25ae373e46c0714d60831e110d31 (patch)
treed69fa50bdf3dffe00a6389e4fbf7c9cd32739618 /insns.h
parent8fa0d037f33beaca5d7823b496ed989d55bea892 (diff)
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Add support for the new instructions in Prescott
Diffstat (limited to 'insns.h')
-rw-r--r--insns.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/insns.h b/insns.h
index 3fb2d84..e2f1145 100644
--- a/insns.h
+++ b/insns.h
@@ -77,6 +77,7 @@ struct itemplate {
#define IF_3DNOW 0x00008000UL /* it's a 3DNow! instruction */
#define IF_SSE 0x00010000UL /* it's a SSE (KNI, MMX2) instruction */
#define IF_SSE2 0x00020000UL /* it's a SSE2 instruction */
+#define IF_SSE3 0x00040000UL /* it's a SSE3 (PNI) instruction */
#define IF_PMASK 0xFF000000UL /* the mask for processor types */
#define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */
/* also the highest possible processor */
@@ -90,6 +91,7 @@ struct itemplate {
#define IF_P6 0x06000000UL /* P6 instruction */
#define IF_KATMAI 0x07000000UL /* Katmai instructions */
#define IF_WILLAMETTE 0x08000000UL /* Willamette instructions */
+#define IF_PRESCOTT 0x09000000UL /* Prescott instructions */
#define IF_IA64 0x0F000000UL /* IA64 instructions */
#define IF_CYRIX 0x10000000UL /* Cyrix-specific instruction */
#define IF_AMD 0x20000000UL /* AMD-specific instruction */