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| author | Jin Kyu Song <jin.kyu.song@intel.com> | 2013-09-13 14:12:57 -0700 |
|---|---|---|
| committer | Cyrill Gorcunov <gorcunov@gmail.com> | 2013-09-14 01:27:10 +0400 |
| commit | eb595942b2c9421548d110e511d12823f38cffbf (patch) | |
| tree | 61c470c56634bcfe31b4519eb9870d20c9c8d157 /insns.h | |
| parent | dd1c0c13c80aa9b034dc3755e2ccc451c63ec6a4 (diff) | |
| download | nasm-eb595942b2c9421548d110e511d12823f38cffbf.tar.gz nasm-eb595942b2c9421548d110e511d12823f38cffbf.tar.bz2 nasm-eb595942b2c9421548d110e511d12823f38cffbf.zip | |
AVX-512: Added AVX-512PF instructions
Added Prefetch (AVX-512PF) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512PF[bit 26] = 1.
CPUID feature flag for PREFETCHWT1 is TBD
but PREFETCHWT1 is included in this commit.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Diffstat (limited to 'insns.h')
| -rw-r--r-- | insns.h | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -130,6 +130,7 @@ extern const uint8_t nasm_bytecodes[]; #define IF_INVPCID 0x1500000000UL /* HACK NEED TO REORGANIZE THESE BITS */ #define IF_AVX512CD (0x1600000000UL|IF_AVX512) /* AVX-512 Conflict Detection insns */ #define IF_AVX512ER (0x1700000000UL|IF_AVX512) /* AVX-512 Exponential and Reciprocal */ +#define IF_AVX512PF (0x1800000000UL|IF_AVX512) /* AVX-512 Prefetch instructions */ #define IF_INSMASK 0xFF00000000UL /* the mask for instruction set types */ #define IF_PMASK 0xFF000000UL /* the mask for processor types */ #define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */ |