diff options
| author | H. Peter Anvin <hpa@zytor.com> | 2008-10-05 19:42:55 -0700 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2008-10-06 18:47:29 -0700 |
| commit | e9d7f1a074d625018f7b42060ba3c341ea723967 (patch) | |
| tree | cb27dcee1733417c2563f368d4eee569662b3a9f /insns.dat | |
| parent | 733cbb3197022811cff2da03f6ebba0a94c3423d (diff) | |
| download | nasm-e9d7f1a074d625018f7b42060ba3c341ea723967.tar.gz nasm-e9d7f1a074d625018f7b42060ba3c341ea723967.tar.bz2 nasm-e9d7f1a074d625018f7b42060ba3c341ea723967.zip | |
Better warnings for out-of-range values
Issue better warnings for out-of-range values. This is not yet
complete.
In particular, note we may have out-of-range for values that end up
being subject to optimization. That is because the optimization takes
place on the *truncated* value, not the pre-truncated value.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'insns.dat')
| -rw-r--r-- | insns.dat | 24 |
1 files changed, 0 insertions, 24 deletions
@@ -61,11 +61,8 @@ ADC rm16,imm8 \320\1\x83\202\15 8086 ADC rm32,imm8 \321\1\x83\202\15 386 ADC rm64,imm8 \324\1\x83\202\15 X64 ADC reg_al,imm \1\x14\21 8086,SM -ADC reg_ax,sbyte16 \320\1\x83\202\15 8086,SM,ND ADC reg_ax,imm \320\1\x15\31 8086,SM -ADC reg_eax,sbyte32 \321\1\x83\202\15 386,SM,ND ADC reg_eax,imm \321\1\x15\41 386,SM -ADC reg_rax,sbyte64 \324\1\x83\202\15 X64,SM,ND ADC reg_rax,imm \324\1\x15\41 X64,SM ADC rm8,imm \1\x80\202\21 8086,SM ADC rm16,imm \320\145\x81\202\141 8086,SM @@ -94,11 +91,8 @@ ADD rm16,imm8 \320\1\x83\200\15 8086 ADD rm32,imm8 \321\1\x83\200\15 386 ADD rm64,imm8 \324\1\x83\200\15 X64 ADD reg_al,imm \1\x04\21 8086,SM -ADD reg_ax,sbyte16 \320\1\x83\200\15 8086,SM,ND ADD reg_ax,imm \320\1\x05\31 8086,SM -ADD reg_eax,sbyte32 \321\1\x83\200\15 386,SM,ND ADD reg_eax,imm \321\1\x05\41 386,SM -ADD reg_rax,sbyte64 \324\1\x83\200\15 X64,SM,ND ADD reg_rax,imm \324\1\x05\41 X64,SM ADD rm8,imm \1\x80\200\21 8086,SM ADD rm16,imm \320\145\x81\200\141 8086,SM @@ -127,11 +121,8 @@ AND rm16,imm8 \320\1\x83\204\15 8086 AND rm32,imm8 \321\1\x83\204\15 386 AND rm64,imm8 \324\1\x83\204\15 X64 AND reg_al,imm \1\x24\21 8086,SM -AND reg_ax,sbyte16 \320\1\x83\204\15 8086,SM,ND AND reg_ax,imm \320\1\x25\31 8086,SM -AND reg_eax,sbyte32 \321\1\x83\204\15 386,SM,ND AND reg_eax,imm \321\1\x25\41 386,SM -AND reg_rax,sbyte64 \324\1\x83\204\15 X64,SM,ND AND reg_rax,imm \324\1\x25\41 X64,SM AND rm8,imm \1\x80\204\21 8086,SM AND rm16,imm \320\145\x81\204\141 8086,SM @@ -255,11 +246,8 @@ CMP rm16,imm8 \320\1\x83\207\15 8086 CMP rm32,imm8 \321\1\x83\207\15 386 CMP rm64,imm8 \324\1\x83\207\15 X64 CMP reg_al,imm \1\x3C\21 8086,SM -CMP reg_ax,sbyte16 \320\1\x83\207\15 8086,SM,ND CMP reg_ax,imm \320\1\x3D\31 8086,SM -CMP reg_eax,sbyte32 \321\1\x83\207\15 386,SM,ND CMP reg_eax,imm \321\1\x3D\41 386,SM -CMP reg_rax,sbyte64 \324\1\x83\207\15 X64,SM,ND CMP reg_rax,imm \324\1\x3D\41 X64,SM CMP rm8,imm \1\x80\207\21 8086,SM CMP rm16,imm \320\145\x81\207\141 8086,SM @@ -856,11 +844,8 @@ OR rm16,imm8 \320\1\x83\201\15 8086 OR rm32,imm8 \321\1\x83\201\15 386 OR rm64,imm8 \324\1\x83\201\15 X64 OR reg_al,imm \1\x0C\21 8086,SM -OR reg_ax,sbyte16 \320\1\x83\201\15 8086,SM,ND OR reg_ax,imm \320\1\x0D\31 8086,SM -OR reg_eax,sbyte32 \321\1\x83\201\15 386,SM,ND OR reg_eax,imm \321\1\x0D\41 386,SM -OR reg_rax,sbyte64 \324\1\x83\201\15 X64,SM,ND OR reg_rax,imm \324\1\x0D\41 X64,SM OR rm8,imm \1\x80\201\21 8086,SM OR rm16,imm \320\145\x81\201\141 8086,SM @@ -1111,11 +1096,8 @@ SBB rm16,imm8 \320\1\x83\203\15 8086 SBB rm32,imm8 \321\1\x83\203\15 386 SBB rm64,imm8 \324\1\x83\203\15 X64 SBB reg_al,imm \1\x1C\21 8086,SM -SBB reg_ax,sbyte16 \320\1\x83\203\15 8086,SM,ND SBB reg_ax,imm \320\1\x1D\31 8086,SM -SBB reg_eax,sbyte32 \321\1\x83\203\15 386,SM,ND SBB reg_eax,imm \321\1\x1D\41 386,SM -SBB reg_rax,sbyte64 \324\1\x83\203\15 X64,SM,ND SBB reg_rax,imm \324\1\x1D\41 X64,SM SBB rm8,imm \1\x80\203\21 8086,SM SBB rm16,imm \320\145\x81\203\141 8086,SM @@ -1227,11 +1209,8 @@ SUB rm16,imm8 \320\1\x83\205\15 8086 SUB rm32,imm8 \321\1\x83\205\15 386 SUB rm64,imm8 \324\1\x83\205\15 X64 SUB reg_al,imm \1\x2C\21 8086,SM -SUB reg_ax,sbyte16 \320\1\x83\205\15 8086,SM,ND SUB reg_ax,imm \320\1\x2D\31 8086,SM -SUB reg_eax,sbyte32 \321\1\x83\205\15 386,SM,ND SUB reg_eax,imm \321\1\x2D\41 386,SM -SUB reg_rax,sbyte64 \324\1\x83\205\15 X64,SM,ND SUB reg_rax,imm \324\1\x2D\41 X64,SM SUB rm8,imm \1\x80\205\21 8086,SM SUB rm16,imm \320\145\x81\205\141 8086,SM @@ -1358,11 +1337,8 @@ XOR rm16,imm8 \320\1\x83\206\15 8086 XOR rm32,imm8 \321\1\x83\206\15 386 XOR rm64,imm8 \324\1\x83\206\15 X64 XOR reg_al,imm \1\x34\21 8086,SM -XOR reg_ax,sbyte16 \320\1\x83\206\15 8086,SM,ND XOR reg_ax,imm \320\1\x35\31 8086,SM -XOR reg_eax,sbyte32 \321\1\x83\206\15 386,SM,ND XOR reg_eax,imm \321\1\x35\41 386,SM -XOR reg_rax,sbyte64 \324\1\x83\206\15 X64,SM,ND XOR reg_rax,imm \324\1\x35\41 X64,SM XOR rm8,imm \1\x80\206\21 8086,SM XOR rm16,imm \320\145\x81\206\141 8086,SM |