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| author | H. Peter Anvin <hpa@zytor.com> | 2002-04-30 20:57:38 +0000 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2002-04-30 20:57:38 +0000 |
| commit | 620515ab4e66b45f9440cf04a1fa61869275170f (patch) | |
| tree | 4acce4f19447ce789254e3ba213d894481a76adc /insns.dat | |
| parent | cd08b15c28d27843722fc26cdf6f77f9082efe62 (diff) | |
| download | nasm-620515ab4e66b45f9440cf04a1fa61869275170f.tar.gz nasm-620515ab4e66b45f9440cf04a1fa61869275170f.tar.bz2 nasm-620515ab4e66b45f9440cf04a1fa61869275170f.zip | |
NASM 0.98p6
Diffstat (limited to 'insns.dat')
| -rw-r--r-- | insns.dat | 11 |
1 files changed, 8 insertions, 3 deletions
@@ -9,7 +9,11 @@ ; line. Hence `void' for no-operand instructions, and `\0' for such ; as EQU. If the last three fields are all `ignore', no action is ; taken except to register the opcode as being present. - +; +; For a detailed description of the code string (third field), please +; see the comment at the top of assemble.c. For a detailed description +; of the flags (fourth field), please see insns.h. +; AAA void \1\x37 8086 AAD void \2\xD5\x0A 8086 AAD imm \1\xD5\24 8086,SB @@ -1271,10 +1275,11 @@ PAVGB mmxreg,mem \301\2\x0F\xE0\110 KATMAI,MMX,SM PAVGW mmxreg,mmxreg \2\x0F\xE3\110 KATMAI,MMX PAVGW mmxreg,mem \301\2\x0F\xE3\110 KATMAI,MMX,SM PEXTRW reg32,mmxreg,imm8 \2\x0F\xC5\110\22 KATMAI,MMX -; This is documented as using a reg32, but it's really using only 16 bits -- accept either +; PINSRW is documented as using a reg32, but it's really using only 16 bit +; -- accept either PINSRW mmxreg,reg16,imm8 \2\x0F\xC4\110\22 KATMAI,MMX PINSRW mmxreg,reg32,imm8 \2\x0F\xC4\110\22 KATMAI,MMX -PINSRW mmxreg,mem16,imm8 \301\2\x0F\xC4\110\22 KATMAI,MMX,SM +PINSRW mmxreg,mem16,imm8 \301\2\x0F\xC4\110\22 KATMAI,MMX PMAXSW mmxreg,mmxreg \2\x0F\xEE\110 KATMAI,MMX PMAXSW mmxreg,mem \301\2\x0F\xEE\110 KATMAI,MMX,SM PMAXUB mmxreg,mmxreg \2\x0F\xDE\110 KATMAI,MMX |