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author | Jin Kyu Song <jin.kyu.song@intel.com> | 2013-11-25 17:59:25 -0800 |
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committer | Jin Kyu Song <jin.kyu.song@intel.com> | 2013-11-27 15:43:32 -0800 |
commit | 1ab16e46731678dd965c9e1148e62c944d9c5ed6 (patch) | |
tree | 0cf62651277618c0462418781549c05403f289cd /doc/nasmdoc.src | |
parent | 3143a462c261fb3a4d38ef504e855ebfc1514c6d (diff) | |
download | nasm-1ab16e46731678dd965c9e1148e62c944d9c5ed6.tar.gz nasm-1ab16e46731678dd965c9e1148e62c944d9c5ed6.tar.bz2 nasm-1ab16e46731678dd965c9e1148e62c944d9c5ed6.zip |
doc: Update the change history and nasmdoc
Added the list of features added since 2.10 release.
Nasmdoc is also updated with those new features.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Diffstat (limited to 'doc/nasmdoc.src')
-rw-r--r-- | doc/nasmdoc.src | 30 |
1 files changed, 27 insertions, 3 deletions
diff --git a/doc/nasmdoc.src b/doc/nasmdoc.src index bfd7593..2ba24c2 100644 --- a/doc/nasmdoc.src +++ b/doc/nasmdoc.src @@ -1213,9 +1213,9 @@ an identifier is 4095 characters. The instruction field may contain any machine instruction: Pentium and P6 instructions, FPU instructions, MMX instructions and even undocumented instructions are all supported. The instruction may be -prefixed by \c{LOCK}, \c{REP}, \c{REPE}/\c{REPZ} or -\c{REPNE}/\c{REPNZ}, in the usual way. Explicit \I{address-size -prefixes}address-size and \i{operand-size prefixes} \i\c{A16}, +prefixed by \c{LOCK}, \c{REP}, \c{REPE}/\c{REPZ}, \c{REPNE}/\c{REPNZ}, +\c{XACQUIRE}/\c{XRELEASE} or \c{BND}, in the usual way. Explicit +\I{address-size prefixes}address-size and \i{operand-size prefixes} \i\c{A16}, \i\c{A32}, \i\c{A64}, \i\c{O16} and \i\c{O32}, \i\c{O64} are provided - one example of their use is given in \k{mixsize}. You can also use the name of a \I{segment override}segment register as an instruction prefix: coding @@ -1462,6 +1462,30 @@ In 64-bit mode, NASM will by default generate absolute addresses. The this is frequently the normally desired behaviour, see the \c{DEFAULT} directive (\k{default}). The keyword \i\c{ABS} overrides \i\c{REL}. +A new form of split effective addres syntax is also supported. This is mainly +intended for mib operand but can be used for any memory reference. The basic +concept of this form is splitting base and index. + +\c mov eax,[ebx+8,ecx*4] ; ebx=base, ecx=index, 4=scale, 8=disp + +For mib operands, there are several ways of writing effective address depending +on the tools. NASM supports all currently possible ways of mib syntax: + +\c ; bndstx +\c ; next 5 lines are parsed same +\c ; base=rax, index=rbx, scale=1, displacement=3 +\c bndstx [rax+0x3,rbx], bnd0 ; NASM - split EA +\c bndstx [rbx*1+rax+0x3], bnd0 ; GAS - '*1' indecates an index reg +\c bndstx [rax+rbx+3], bnd0 ; GAS - without hints +\c bndstx [rax+0x3], bnd0, rbx ; ICC-1 +\c bndstx [rax+0x3], rbx, bnd0 ; ICC-2 + +When broadcasting decorator is used, the opsize keyword should match +the size of each element. + +\c VDIVPS zmm4, zmm5, dword [rbx]{1to16} ; single-precision float +\c VDIVPS zmm4, zmm5, zword [rbx] ; packed 512 bit memory + \H{const} \i{Constants} |