Add np and similar prefixes to instructions that should have them

This adds "np" to a bunch of SSE-style instructions that should have
it, "norep" (which was implemented but unused) on quasi-SSE instructions
that use F2 and F3 as instruction extensions but 66 for operand size,
"nof3" (newly implemented) on a few instructions, "norexw" on some
instructions that have only 32-bit and 64-bit versions, and one NOLONG.

It also removes some incorrect "np"s, changes some "f3"s to "f3i"s,
and fixes the decoding of the XCHG/NOP/PAUSE mess: F390 is always
PAUSE even when rex.b=1 (at least according to XED).

Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/assemble.c b/assemble.c
index 4f791ec..7b33df9 100644
--- a/assemble.c
+++ b/assemble.c
@@ -118,6 +118,8 @@
  * \323          - indicates fixed 64-bit operand size, REX on extensions only.
  * \324          - indicates 64-bit operand size requiring REX prefix.
  * \325          - instruction which always uses spl/bpl/sil/dil
+ * \326          - instruction not valid with 0xF3 REP prefix.  Hint for
+                   disassembler only; for SSE instructions.
  * \330          - a literal byte follows in the code stream, to be added
  *                 to the condition code value of the instruction.
  * \331          - instruction not valid with REP prefix.  Hint for
@@ -1061,6 +1063,9 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
             ins->rex |= REX_NH;
             break;
 
+        case 0326:
+            break;
+
         case 0330:
             codes++, length++;
             break;
@@ -1709,6 +1714,9 @@ static void gencode(int32_t segment, int64_t offset, int bits,
         case 0325:
             break;
 
+        case 0326:
+            break;
+
         case 0330:
             *bytes = *codes++ ^ condval[ins->condition];
             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);