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| author | H. Peter Anvin <hpa@zytor.com> | 2008-02-14 11:25:14 -0800 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2008-02-14 11:25:36 -0800 |
| commit | f6c51f084bbac16aec7c4f536542297030f17348 (patch) | |
| tree | c2a0ac7abd7a4b3f0d43b69614d363df875f1624 | |
| parent | f0b43d212e77012641524570dd55b925bbea9c15 (diff) | |
| download | nasm-f6c51f084bbac16aec7c4f536542297030f17348.tar.gz nasm-f6c51f084bbac16aec7c4f536542297030f17348.tar.bz2 nasm-f6c51f084bbac16aec7c4f536542297030f17348.zip | |
Add XSAVE instruction features (CPU feature is bogus, but oh well.)
Add the XSAVE group of instructions: XSAVE, XRSTOR, XGETBV, XSETBV.
The CPU feature information is bogus, but so is our entire handling of
CPU feature sets for anything but the bare necessities (long jump
emulation, etc.)
| -rw-r--r-- | insns.dat | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -1464,6 +1464,13 @@ XORPS xmmreg,xmmrm \2\x0F\x57\110 KATMAI,SSE FXRSTOR mem \2\x0F\xAE\201 P6,SSE,FPU FXSAVE mem \2\x0F\xAE\200 P6,SSE,FPU +; Introduced in ??? ... we really need to clean up the handling +; of CPU feature bits. +XGETBV void \3\x0F\x01\xD0 NEHALEM,PRIV +XSETBV void \3\x0F\x01\xD1 NEHALEM,PRIV +XSAVE mem \2\x0F\xAE\204 NEHALEM +XRSTOR mem \2\x0F\xAE\205 NEHALEM + ; These instructions are not SSE-specific; they are ;# Generic memory operations ; and work even if CR4.OSFXFR == 0 |