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| author | H. Peter Anvin <hpa@linux.intel.com> | 2014-02-18 14:05:14 -0800 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2014-02-18 14:05:14 -0800 |
| commit | f2d2569bb6cd5b46770e3427aff17be307f37c9a (patch) | |
| tree | b9e2942f780ebaeb677c40e0272dcd458e71df59 | |
| parent | 0ace62cb6a45b2cd710220a82a9b197c9e30b4f9 (diff) | |
| download | nasm-f2d2569bb6cd5b46770e3427aff17be307f37c9a.tar.gz nasm-f2d2569bb6cd5b46770e3427aff17be307f37c9a.tar.bz2 nasm-f2d2569bb6cd5b46770e3427aff17be307f37c9a.zip | |
changes.src: changelog for 2.11.01
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
| -rw-r--r-- | doc/changes.src | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/doc/changes.src b/doc/changes.src index ba3e7d3..f4b2842 100644 --- a/doc/changes.src +++ b/doc/changes.src @@ -7,6 +7,19 @@ The NASM 2 series supports x86-64, and is the production version of NASM since 2007. +\S{cl-2.11.01} Version 2.11.01 + +\b Allow instructions which implicitly uses \c{XMM0} (\c{VBLENDVPD}, +\c{VBLENDVPS}, \c{PBLENDVB} and \c{SHA256RNDS2}) to be specified +without an explicit \c{xmm0} on the assembly line. In other words, +the following two lines produce the same output: + +\c vblendvpd xmm2,xmm1,xmm0 ; Last operand is fixed xmm0 +\c vblendvpd xmm2,xmm1 ; Implicit xmm0 omitted + +\b In the ELF backends, don't crash the assembler if \c{section align} +is specified without a value. + \S{cl-2.11} Version 2.11 \b Add support for the Intel AVX-512 instruction set: |