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| author | Jin Kyu Song <jin.kyu.song@intel.com> | 2013-10-15 19:44:03 -0700 |
|---|---|---|
| committer | Jin Kyu Song <jin.kyu.song@intel.com> | 2013-11-20 11:29:42 -0800 |
| commit | da1a5cd5145f8dc67d00589af73a956627d1ac54 (patch) | |
| tree | e5fe57ccfaec89623ee85a3f3b64e4dae4aed140 | |
| parent | 40762afbe8706e00e837c802994c4e52ba3e3884 (diff) | |
| download | nasm-da1a5cd5145f8dc67d00589af73a956627d1ac54.tar.gz nasm-da1a5cd5145f8dc67d00589af73a956627d1ac54.tar.bz2 nasm-da1a5cd5145f8dc67d00589af73a956627d1ac54.zip | |
SHA: Add SHA instructions
New instruction extensions of SHA family are added.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
| -rw-r--r-- | insns.dat | 9 | ||||
| -rw-r--r-- | insns.h | 1 |
2 files changed, 10 insertions, 0 deletions
@@ -4171,6 +4171,15 @@ BNDSTX mem128,bndreg [mr: 0f 1b /r ] MPX,MIB,SO,FUTURE BNDSTX mem128,reg64,bndreg [mxr: 0f 1b /r ] MPX,MIB,FUTURE BNDSTX mem128,bndreg,reg64 [mrx: 0f 1b /r ] MPX,MIB,FUTURE +; SHA instructions +SHA1RNDS4 xmmreg,xmmrm128,imm8 [rmi: 0f 3a cc /r ib ] SHA,FUTURE +SHA1NEXTE xmmreg,xmmrm128 [rm: 0f 38 c8 /r ] SHA,FUTURE +SHA1MSG1 xmmreg,xmmrm128 [rm: 0f 38 c9 /r ] SHA,FUTURE +SHA1MSG2 xmmreg,xmmrm128 [rm: 0f 38 ca /r ] SHA,FUTURE +SHA256RNDS2 xmmreg,xmmrm128,xmm0 [rm-: 0f 38 cb /r ] SHA,FUTURE +SHA256MSG1 xmmreg,xmmrm128 [rm: 0f 38 cc /r ] SHA,FUTURE +SHA256MSG2 xmmreg,xmmrm128 [rm: 0f 38 cd /r ] SHA,FUTURE + ;# Systematic names for the hinting nop instructions ; These should be last in the file HINT_NOP0 rm16 [m: o16 0f 18 /0] P6,UNDOC @@ -133,6 +133,7 @@ extern const uint8_t nasm_bytecodes[]; #define IF_AVX512ER (0x1700000000UL|IF_AVX512) /* AVX-512 Exponential and Reciprocal */ #define IF_AVX512PF (0x1800000000UL|IF_AVX512) /* AVX-512 Prefetch instructions */ #define IF_MPX 0x1900000000UL /* MPX instructions */ +#define IF_SHA 0x1A00000000UL /* SHA instructions */ #define IF_INSMASK 0xFF00000000UL /* the mask for instruction set types */ #define IF_PMASK 0xFF000000UL /* the mask for processor types */ #define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */ |