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| author | Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> | 2023-03-17 14:42:19 +0100 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2023-04-25 06:47:11 +0000 |
| commit | dc5a9e176c2aef61ec025f116490b135cd7b9af4 (patch) | |
| tree | 66483f2964d34d6a90e166552ceeb0ddf6d4250d /include | |
| parent | 171d31640262020af5b45d62839701dba45f44cf (diff) | |
| download | mesa-dc5a9e176c2aef61ec025f116490b135cd7b9af4.tar.gz mesa-dc5a9e176c2aef61ec025f116490b135cd7b9af4.tar.bz2 mesa-dc5a9e176c2aef61ec025f116490b135cd7b9af4.zip | |
amd: update amdgpu_drm.h
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986>
Diffstat (limited to 'include')
| -rw-r--r-- | include/drm-uapi/amdgpu_drm.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h index b6eb90df5d0..72041a51cc2 100644 --- a/include/drm-uapi/amdgpu_drm.h +++ b/include/drm-uapi/amdgpu_drm.h @@ -592,6 +592,7 @@ struct drm_amdgpu_gem_va { #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 +#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a struct drm_amdgpu_cs_chunk { __u32 chunk_id; @@ -708,6 +709,15 @@ struct drm_amdgpu_cs_chunk_data { }; }; +#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 + +struct drm_amdgpu_cs_chunk_cp_gfx_shadow { + __u64 shadow_va; + __u64 csa_va; + __u64 gds_va; + __u64 flags; +}; + /* * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU * @@ -1126,6 +1136,14 @@ struct drm_amdgpu_info_device { __u64 mall_size; /* AKA infinity cache */ /* high 32 bits of the rb pipes mask */ __u32 enabled_rb_pipes_mask_hi; + /* shadow area size for gfx11 */ + __u32 shadow_size; + /* shadow area base virtual alignment for gfx11 */ + __u32 shadow_alignment; + /* context save area size for gfx11 */ + __u32 csa_size; + /* context save area base virtual alignment for gfx11 */ + __u32 csa_alignment; }; struct drm_amdgpu_info_hw_ip { |