From f94292711cdf06e9f9e52f4f691e4bb6faf5b91d Mon Sep 17 00:00:00 2001
From: kyukhin <kyukhin@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Fri, 15 Apr 2016 09:36:31 +0000
Subject: AVX-512. Use proper mem ops modifier for Intel syntax in broadcast
 patter.

PR target/70662
gcc/
	* config/i386/sse.md: Use proper memory operand
	modifiers.
gcc/testsuite.
	* gcc.target/i386/pr70662.c: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-5-branch@235013 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog                           |  6 ++++++
 gcc/config/i386/sse.md                  | 12 +++++++++++-
 gcc/testsuite/ChangeLog                 |  5 +++++
 gcc/testsuite/gcc.target/i386/pr70662.c | 19 +++++++++++++++++++
 4 files changed, 41 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr70662.c

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f6cb067a3d8..a591d219c25 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2016-04-15  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+	PR target/70662
+	* config/i386/sse.md: Use proper memory operand
+	modifiers.
+
 2016-04-14  Nick Clifton  <nickc@redhat.com>
             Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index f3a08d874d1..9f974394ae2 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -16658,7 +16658,17 @@
 	    (match_operand:<ssexmmmode> 1 "nonimmediate_operand" "vm")
 	    (parallel [(const_int 0)]))))]
   "TARGET_AVX512F"
-  "v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+{
+  /*  There is no DF broadcast (in AVX-512*) to 128b register.
+      Mimic it with integer variant.  */
+  if (<MODE>mode == V2DFmode)
+    return "vpbroadcastq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}";
+
+  if (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 32)
+    return "v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %k1}";
+   else
+    return "v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}";
+}
   [(set_attr "type" "ssemov")
    (set_attr "prefix" "evex")
    (set_attr "mode" "<sseinsnmode>")])
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 12bda055379..de4fa5384e0 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-04-15  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+	PR target/70662
+	* gcc.target/i386/pr70662.c: New test.
+
 2016-04-14  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	Backport from mainline
diff --git a/gcc/testsuite/gcc.target/i386/pr70662.c b/gcc/testsuite/gcc.target/i386/pr70662.c
new file mode 100644
index 00000000000..109e224d7b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70662.c
@@ -0,0 +1,19 @@
+/* { dg-do assemble { target { ! ia32 } } } */
+/* { dg-require-effective-target avx512vbmi } */
+/* { dg-require-effective-target masm_intel } */
+/* { dg-options "-Og -fschedule-insns -fno-tree-fre -mavx512vbmi --param=max-sched-ready-insns=1 -masm=intel" } */
+
+typedef char v64u8 __attribute__((vector_size(64)));
+typedef int v64u32 __attribute__((vector_size(64)));
+typedef long v64u64 __attribute__((vector_size(64)));
+typedef __int128 v64u128 __attribute__((vector_size(64)));
+
+v64u128
+foo(int u8_0, unsigned u128_0, v64u32 v64u32_1, v64u32 v64u32_0, v64u64 v64u64_0, v64u128 v64u128_0)
+{
+  v64u8 v64u8_0 = v64u8_0;
+  v64u32_0 = v64u32_0 >> (v64u32){0, 0, 0, 1, 0, ((v64u64)v64u64_0)[u8_0], ((v64u32)v64u128_0)[15], 0, 0, 0, 0, 4, ((v64u64)v64u64_0)[v64u32_0[0]] - 1};
+  v64u8_0 = v64u8_0 << ((v64u8)v64u32_1 & 1);
+  v64u64_0[0] >>= 0;
+  return u128_0 + (v64u128)v64u8_0 + (v64u128)v64u32_0 + (v64u128)v64u64_0;
+}
-- 
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