diff options
Diffstat (limited to 'gcc')
29 files changed, 299 insertions, 37 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8b0fa4b502f..c0f56a156b0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,57 @@ +2014-04-22 Release Manager + + * GCC 4.9.0 released. + +2014-04-18 Richard Henderson <rth@redhat.com> + + * config/aarch64/aarch64.c (aarch64_register_move_cost): Pass a mode + to GET_MODE_SIZE, not a reg_class_t. + +2014-04-17 Jakub Jelinek <jakub@redhat.com> + + PR target/60847 + Forward port from 4.8 branch + 2013-07-19 Kirill Yukhin <kirill.yukhin@intel.com> + + * config/i386/bmiintrin.h (_blsi_u32): New. + (_blsi_u64): Ditto. + (_blsr_u32): Ditto. + (_blsr_u64): Ditto. + (_blsmsk_u32): Ditto. + (_blsmsk_u64): Ditto. + (_tzcnt_u32): Ditto. + (_tzcnt_u64): Ditto. + +2014-04-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + PR target/60839 + Revert the following patch + + 2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/60735 + * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have + software floating point or no floating point registers, do not + allow any type in the FPRs. Eliminate a test for SPE SIMD types + in GPRs that occurs after we tested for GPRs that would never be + true. + + * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64): + Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE, + since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE, + specifically allow DDmode, since that does not use the SPE SIMD + instructions. + +2014-04-15 Jakub Jelinek <jakub@redhat.com> + + PR plugins/59335 + * Makefile.in (PLUGIN_HEADERS): Add various headers that have been + added in 4.9. + +2014-04-14 Yufeng Zhang <yufeng.zhang@arm.com> + + * doc/invoke.texi (free): Document AArch64. + 2013-04-11 Jakub Jelinek <jakub@redhat.com> * DEV-PHASE: Set to prerelease. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 98f6999a71a..50894d11578 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20140414 +20140422 diff --git a/gcc/DEV-PHASE b/gcc/DEV-PHASE index 373fbc60bb9..e69de29bb2d 100644 --- a/gcc/DEV-PHASE +++ b/gcc/DEV-PHASE @@ -1 +0,0 @@ -prerelease diff --git a/gcc/Makefile.in b/gcc/Makefile.in index 660616eeaf8..d1ab22f1902 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -3125,7 +3125,14 @@ PLUGIN_HEADERS = $(TREE_H) $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ version.h stringpool.h gimplify.h gimple-iterator.h gimple-ssa.h \ fold-const.h tree-cfg.h tree-into-ssa.h tree-ssanames.h print-tree.h \ varasm.h context.h tree-phinodes.h stor-layout.h ssa-iterators.h \ - $(RESOURCE_H) tree-cfgcleanup.h + $(RESOURCE_H) tree-cfgcleanup.h attribs.h calls.h cfgexpand.h \ + diagnostic-color.h gcc-symtab.h gimple-builder.h gimple-low.h \ + gimple-walk.h gimplify-me.h pass_manager.h print-rtl.h stmt.h \ + tree-dfa.h tree-hasher.h tree-nested.h tree-object-size.h tree-outof-ssa.h \ + tree-parloops.h tree-ssa-address.h tree-ssa-coalesce.h tree-ssa-dom.h \ + tree-ssa-loop.h tree-ssa-loop-ivopts.h tree-ssa-loop-manip.h \ + tree-ssa-loop-niter.h tree-ssa-ter.h tree-ssa-threadedge.h \ + tree-ssa-threadupdate.h # generate the 'build fragment' b-header-vars s-header-vars: Makefile diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index b89bfec2aa7..b4d3e77699d 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,7 @@ +2014-04-22 Release Manager + + * GCC 4.9.0 released. + 2014-04-09 Eric Botcazou <ebotcazou@adacore.com> Svante Signell <svante.signell@gmail.com> diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 152c3b7def3..805ba9ca8c7 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,13 @@ +2014-04-22 Release Manager + + * GCC 4.9.0 released. + +2014-04-15 Igor Zamyatin <igor.zamyatin@intel.com> + + PR middle-end/60467 + * cilk.c (cilk_set_spawn_marker): Remove FUNCTION_DECL + as possible argument for Cilk_spawn. + 2014-04-08 Marek Polacek <polacek@redhat.com> PR sanitizer/60745 diff --git a/gcc/c-family/cilk.c b/gcc/c-family/cilk.c index 6a7bf4f1efa..bf549ad1791 100644 --- a/gcc/c-family/cilk.c +++ b/gcc/c-family/cilk.c @@ -99,7 +99,6 @@ cilk_set_spawn_marker (location_t loc, tree fcall) it. */ return false; else if (TREE_CODE (fcall) != CALL_EXPR - && TREE_CODE (fcall) != FUNCTION_DECL /* In C++, TARGET_EXPR is generated when we have an overloaded '=' operator. */ && TREE_CODE (fcall) != TARGET_EXPR) diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index 6b819e9964d..f5e7179e911 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,17 @@ +2014-04-22 Release Manager + + * GCC 4.9.0 released. + +2014-04-15 Igor Zamyatin <igor.zamyatin@intel.com> + + PR middle-end/60469 + * c-array-notation.c (fix_builtin_array_notation_fn): Use + create_tmp_var instead build_decl for creating temps. + (build_array_notation_expr): Likewise. + (fix_conditional_array_notations_1): Likewise. + (fix_array_notation_expr): Likewise. + (fix_array_notation_call_expr): Likewise. + 2014-03-28 Jakub Jelinek <jakub@redhat.com> PR c++/60689 diff --git a/gcc/c/c-array-notation.c b/gcc/c/c-array-notation.c index 6a5631c3b6f..0ac6ba8e119 100644 --- a/gcc/c/c-array-notation.c +++ b/gcc/c/c-array-notation.c @@ -70,6 +70,7 @@ #include "coretypes.h" #include "tree.h" #include "c-tree.h" +#include "gimple-expr.h" #include "tree-iterator.h" #include "opts.h" #include "c-family/c-common.h" @@ -282,8 +283,7 @@ fix_builtin_array_notation_fn (tree an_builtin_fn, tree *new_var) for (ii = 0; ii < rank; ii++) { - an_loop_info[ii].var = build_decl (location, VAR_DECL, NULL_TREE, - integer_type_node); + an_loop_info[ii].var = create_tmp_var (integer_type_node, NULL); an_loop_info[ii].ind_init = build_modify_expr (location, an_loop_info[ii].var, TREE_TYPE (an_loop_info[ii].var), NOP_EXPR, @@ -781,8 +781,8 @@ build_array_notation_expr (location_t location, tree lhs, tree lhs_origtype, for (ii = 0; ii < lhs_rank; ii++) if (lhs_an_info[0][ii].is_vector) { - lhs_an_loop_info[ii].var = build_decl (location, VAR_DECL, NULL_TREE, - integer_type_node); + lhs_an_loop_info[ii].var = create_tmp_var (integer_type_node, + NULL); lhs_an_loop_info[ii].ind_init = build_modify_expr (location, lhs_an_loop_info[ii].var, TREE_TYPE (lhs_an_loop_info[ii].var), NOP_EXPR, @@ -793,8 +793,8 @@ build_array_notation_expr (location_t location, tree lhs, tree lhs_origtype, { /* When we have a polynomial, we assume that the indices are of type integer. */ - rhs_an_loop_info[ii].var = build_decl (location, VAR_DECL, NULL_TREE, - integer_type_node); + rhs_an_loop_info[ii].var = create_tmp_var (integer_type_node, + NULL); rhs_an_loop_info[ii].ind_init = build_modify_expr (location, rhs_an_loop_info[ii].var, TREE_TYPE (rhs_an_loop_info[ii].var), NOP_EXPR, @@ -970,8 +970,7 @@ fix_conditional_array_notations_1 (tree stmt) cilkplus_extract_an_triplets (array_list, list_size, rank, &an_info); for (ii = 0; ii < rank; ii++) { - an_loop_info[ii].var = build_decl (location, VAR_DECL, NULL_TREE, - integer_type_node); + an_loop_info[ii].var = create_tmp_var (integer_type_node, NULL); an_loop_info[ii].ind_init = build_modify_expr (location, an_loop_info[ii].var, TREE_TYPE (an_loop_info[ii].var), NOP_EXPR, @@ -1067,8 +1066,7 @@ fix_array_notation_expr (location_t location, enum tree_code code, loop_init = push_stmt_list (); for (ii = 0; ii < rank; ii++) { - an_loop_info[ii].var = build_decl (location, VAR_DECL, NULL_TREE, - integer_type_node); + an_loop_info[ii].var = create_tmp_var (integer_type_node, NULL); an_loop_info[ii].ind_init = build_modify_expr (location, an_loop_info[ii].var, TREE_TYPE (an_loop_info[ii].var), NOP_EXPR, @@ -1163,8 +1161,7 @@ fix_array_notation_call_expr (tree arg) } for (ii = 0; ii < rank; ii++) { - an_loop_info[ii].var = build_decl (location, VAR_DECL, NULL_TREE, - integer_type_node); + an_loop_info[ii].var = create_tmp_var (integer_type_node, NULL); an_loop_info[ii].ind_init = build_modify_expr (location, an_loop_info[ii].var, TREE_TYPE (an_loop_info[ii].var), NOP_EXPR, location, diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index a3147ee092f..7b6c2b38e03 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4847,9 +4847,11 @@ aarch64_address_cost (rtx x ATTRIBUTE_UNUSED, } static int -aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, - reg_class_t from, reg_class_t to) +aarch64_register_move_cost (enum machine_mode mode, + reg_class_t from_i, reg_class_t to_i) { + enum reg_class from = (enum reg_class) from_i; + enum reg_class to = (enum reg_class) to_i; const struct cpu_regmove_cost *regmove_cost = aarch64_tune_params->regmove_cost; @@ -4875,8 +4877,7 @@ aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, secondary reload. A general register is used as a scratch to move the upper DI value and the lower DI value is moved directly, hence the cost is the sum of three moves. */ - - if (! TARGET_SIMD && GET_MODE_SIZE (from) == 128 && GET_MODE_SIZE (to) == 128) + if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 128) return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP; return regmove_cost->FP2FP; diff --git a/gcc/config/i386/bmiintrin.h b/gcc/config/i386/bmiintrin.h index b86adf179cf..b2d7c60eaf8 100644 --- a/gcc/config/i386/bmiintrin.h +++ b/gcc/config/i386/bmiintrin.h @@ -40,7 +40,6 @@ __tzcnt_u16 (unsigned short __X) return __builtin_ctzs (__X); } - extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __andn_u32 (unsigned int __X, unsigned int __Y) { @@ -66,17 +65,34 @@ __blsi_u32 (unsigned int __X) } extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsi_u32 (unsigned int __X) +{ + return __blsi_u32 (__X); +} + +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsmsk_u32 (unsigned int __X) { return __X ^ (__X - 1); } extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsmsk_u32 (unsigned int __X) +{ + return __blsmsk_u32 (__X); +} + +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsr_u32 (unsigned int __X) { return __X & (__X - 1); } +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsr_u32 (unsigned int __X) +{ + return __blsr_u32 (__X); +} extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __tzcnt_u32 (unsigned int __X) @@ -84,6 +100,12 @@ __tzcnt_u32 (unsigned int __X) return __builtin_ctz (__X); } +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_tzcnt_u32 (unsigned int __X) +{ + return __builtin_ctz (__X); +} + #ifdef __x86_64__ extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -111,23 +133,47 @@ __blsi_u64 (unsigned long long __X) } extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsi_u64 (unsigned long long __X) +{ + return __blsi_u64 (__X); +} + +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsmsk_u64 (unsigned long long __X) { return __X ^ (__X - 1); } extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsmsk_u64 (unsigned long long __X) +{ + return __blsmsk_u64 (__X); +} + +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsr_u64 (unsigned long long __X) { return __X & (__X - 1); } extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsr_u64 (unsigned long long __X) +{ + return __blsr_u64 (__X); +} + +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __tzcnt_u64 (unsigned long long __X) { return __builtin_ctzll (__X); } +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_tzcnt_u64 (unsigned long long __X) +{ + return __builtin_ctzll (__X); +} + #endif /* __x86_64__ */ #ifdef __DISABLE_BMI__ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index f82e0a2df6e..494efc562b7 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1752,9 +1752,6 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) modes and DImode. */ if (FP_REGNO_P (regno)) { - if (TARGET_SOFT_FLOAT || !TARGET_FPRS) - return 0; - if (SCALAR_FLOAT_MODE_P (mode) && (mode != TDmode || (regno % 2) == 0) && FP_REGNO_P (last_regno)) @@ -1783,6 +1780,10 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) || mode == V1TImode); + /* ...but GPRs can hold SIMD data on the SPE in one register. */ + if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) + return 1; + /* We cannot put non-VSX TImode or PTImode anywhere except general register and it must be able to fit within the register set. */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 738011c93c9..64c9e7c1006 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -9394,9 +9394,8 @@ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r") (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))] "! TARGET_POWERPC64 - && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) - || TARGET_SOFT_FLOAT - || (<MODE>mode == DDmode && TARGET_E500_DOUBLE)) + && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) + || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" "#" diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index afbf24ace95..f95944b9bd6 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,12 @@ +2014-04-22 Release Manager + + * GCC 4.9.0 released. + +2014-04-15 Jakub Jelinek <jakub@redhat.com> + + PR plugins/59335 + * Make-lang.h (CP_PLUGIN_HEADERS): Add type-utils.h. + 2014-04-10 Richard Biener <rguenther@suse.de> Jakub Jelinek <jakub@redhat.com> diff --git a/gcc/cp/Make-lang.in b/gcc/cp/Make-lang.in index 5480c4eaeb2..bd1c1d78f88 100644 --- a/gcc/cp/Make-lang.in +++ b/gcc/cp/Make-lang.in @@ -39,7 +39,7 @@ CXX_INSTALL_NAME := $(shell echo c++|sed '$(program_transform_name)') GXX_INSTALL_NAME := $(shell echo g++|sed '$(program_transform_name)') CXX_TARGET_INSTALL_NAME := $(target_noncanonical)-$(shell echo c++|sed '$(program_transform_name)') GXX_TARGET_INSTALL_NAME := $(target_noncanonical)-$(shell echo g++|sed '$(program_transform_name)') -CP_PLUGIN_HEADERS := cp-tree.h cxx-pretty-print.h name-lookup.h +CP_PLUGIN_HEADERS := cp-tree.h cxx-pretty-print.h name-lookup.h type-utils.h # # Define the names for selecting c++ in LANGUAGES. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e2fd4c62c18..2d43457c224 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -7390,7 +7390,7 @@ Attempt to remove redundant extension instructions. This is especially helpful for the x86-64 architecture, which implicitly zero-extends in 64-bit registers after writing to their lower 32-bit half. -Enabled for x86 at levels @option{-O2}, @option{-O3}. +Enabled for AArch64 and x86 at levels @option{-O2}, @option{-O3}. @item -flive-range-shrinkage @opindex flive-range-shrinkage diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index b822a7d975b..eb33cc92887 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,7 @@ +2014-04-22 Release Manager + + * GCC 4.9.0 released. + 2014-04-13 Paul Thomas <pault@gcc.gnu.org> PR fortran/58085 diff --git a/gcc/go/ChangeLog b/gcc/go/ChangeLog index 689578e2064..1c1505a386c 100644 --- a/gcc/go/ChangeLog +++ b/gcc/go/ChangeLog @@ -1,3 +1,7 @@ +2014-04-22 Release Manager + + * GCC 4.9.0 released. + 2014-03-03 Ian Lance Taylor <iant@google.com> * go-gcc.cc (Gcc_backend::immutable_struct): If IS_COMMON, set diff --git a/gcc/java/ChangeLog b/gcc/java/ChangeLog index 7bdc8ca2087..c806f62557f 100644 --- a/gcc/java/ChangeLog +++ b/gcc/java/ChangeLog @@ -1,3 +1,7 @@ +2014-04-22 Release Manager + + * GCC 4.9.0 released. + 2014-01-02 Richard Sandiford <rdsandiford@googlemail.com> Update copyright years diff --git a/gcc/lto/ChangeLog b/gcc/lto/ChangeLog index ad806db7d76..b396e485dce 100644 --- a/gcc/lto/ChangeLog +++ b/gcc/lto/ChangeLog @@ -1,3 +1,7 @@ +2014-04-22 Release Manager + + * GCC 4.9.0 released. + 2014-03-19 Richard Biener <rguenther@suse.de> PR middle-end/60553 diff --git a/gcc/objc/ChangeLog b/gcc/objc/ChangeLog index ca9841eed55..de619aeeac5 100644 --- a/gcc/objc/ChangeLog +++ b/gcc/objc/ChangeLog @@ -1,3 +1,7 @@ +2014-04-22 Release Manager + + * GCC 4.9.0 released. + 2014-01-31 Marek Polacek <polacek@redhat.com> PR c/59963 diff --git a/gcc/objcp/ChangeLog b/gcc/objcp/ChangeLog index c4183ea31d2..19f43bc8865 100644 --- a/gcc/objcp/ChangeLog +++ b/gcc/objcp/ChangeLog @@ -1,3 +1,7 @@ +2014-04-22 Release Manager + + * GCC 4.9.0 released. + 2014-01-02 Richard Sandiford <rdsandiford@googlemail.com> Update copyright years diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog index f75f03bb5af..b7e3dfb78c7 100644 --- a/gcc/po/ChangeLog +++ b/gcc/po/ChangeLog @@ -1,3 +1,7 @@ +2014-04-22 Release Manager + + * GCC 4.9.0 released. + 2014-03-31 Joseph Myers <joseph@codesourcery.com> * sv.po: Update. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index eec26c9ee51..4c09a1e0525 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,32 @@ +2014-04-22 Release Manager + + * GCC 4.9.0 released. + +2014-04-17 Jakub Jelinek <jakub@redhat.com> + + PR target/60847 + Forward port from 4.8 branch + 2013-07-19 Kirill Yukhin <kirill.yukhin@intel.com> + + * gcc.target/i386/bmi-1.c: Extend with new instrinsics. + Fix scan patterns. + * gcc.target/i386/bmi-2.c: Ditto. + +2014-04-15 Igor Zamyatin <igor.zamyatin@intel.com> + + PR middle-end/60467 + * c-c++-common/cilk-plus/CK/invalid_spawns.c: Add new invalid + case to check. + +2014-04-15 Igor Zamyatin <igor.zamyatin@intel.com> + + PR middle-end/60469 + * c-c++-common/cilk-plus/CK/pr60469.c: New test. + +2014-04-14 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * gcc.dg/lto/pr55113_0.c: Skip on i?86-*-solaris2.1[0-1]*. + 2014-04-14 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> * lib/target-supports.exp diff --git a/gcc/testsuite/c-c++-common/cilk-plus/CK/invalid_spawns.c b/gcc/testsuite/c-c++-common/cilk-plus/CK/invalid_spawns.c index ba9e6193627..5b43be76010 100644 --- a/gcc/testsuite/c-c++-common/cilk-plus/CK/invalid_spawns.c +++ b/gcc/testsuite/c-c++-common/cilk-plus/CK/invalid_spawns.c @@ -8,6 +8,7 @@ int main (void) { int x; + _Cilk_spawn foo; /* { dg-error "only function calls can be spawned" } */ _Cilk_spawn x; /* { dg-error "only function calls can be spawned" } */ return x; } diff --git a/gcc/testsuite/c-c++-common/cilk-plus/CK/pr60469.c b/gcc/testsuite/c-c++-common/cilk-plus/CK/pr60469.c new file mode 100644 index 00000000000..ca0cf7f68bc --- /dev/null +++ b/gcc/testsuite/c-c++-common/cilk-plus/CK/pr60469.c @@ -0,0 +1,15 @@ +/* PR middle-end/60469 */ +/* { dg-do compile } */ +/* { dg-options "-fcilkplus" } */ + +void foo() {} + +#define ALEN 1024 + +int main(int argc, char* argv[]) +{ + int b[ALEN]; + b[:] = 100; + _Cilk_spawn foo(); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/lto/pr55113_0.c b/gcc/testsuite/gcc.dg/lto/pr55113_0.c index 0477fe41bc8..8c309761bce 100644 --- a/gcc/testsuite/gcc.dg/lto/pr55113_0.c +++ b/gcc/testsuite/gcc.dg/lto/pr55113_0.c @@ -2,6 +2,7 @@ /* { dg-lto-do link } */ /* { dg-lto-options { { -flto -fshort-double -O0 } } }*/ /* { dg-skip-if "PR60410" { x86_64-*-* || { i?86-*-* && lp64 } } } */ +/* { dg-skip-if "PR60410" { i?86-*-solaris2.1[0-9]* } } */ int main(void) diff --git a/gcc/testsuite/gcc.target/i386/bmi-1.c b/gcc/testsuite/gcc.target/i386/bmi-1.c index a05cb275adc..c66a9d83b29 100644 --- a/gcc/testsuite/gcc.target/i386/bmi-1.c +++ b/gcc/testsuite/gcc.target/i386/bmi-1.c @@ -2,10 +2,10 @@ /* { dg-options "-O2 -mbmi " } */ /* { dg-final { scan-assembler "andn\[^\\n]*eax" } } */ /* { dg-final { scan-assembler-times "bextr\[ \\t]+\[^\\n]*eax" 2 } } */ -/* { dg-final { scan-assembler "blsi\[^\\n]*eax" } } */ -/* { dg-final { scan-assembler "blsmsk\[^\\n]*eax" } } */ -/* { dg-final { scan-assembler "blsr\[^\\n]*eax" } } */ -/* { dg-final { scan-assembler "tzcntl\[^\\n]*eax" } } */ +/* { dg-final { scan-assembler-times "blsi\[^\\n]*eax" 2 } } */ +/* { dg-final { scan-assembler-times "blsmsk\[^\\n]*eax" 2 } } */ +/* { dg-final { scan-assembler-times "blsr\[^\\n]*eax" 2 } } */ +/* { dg-final { scan-assembler-times "tzcntl\[^\\n]*eax" 2 } } */ #include <x86intrin.h> @@ -36,19 +36,43 @@ func_blsi32 (unsigned int X) } unsigned int +func_blsi32_2 (unsigned int X) +{ + return _blsi_u32(X); +} + +unsigned int func_blsmsk32 (unsigned int X) { return __blsmsk_u32(X); } unsigned int +func_blsmsk32_2 (unsigned int X) +{ + return _blsmsk_u32(X); +} + +unsigned int func_blsr32 (unsigned int X) { return __blsr_u32(X); } unsigned int +func_blsr32_2 (unsigned int X) +{ + return _blsr_u32(X); +} + +unsigned int func_tzcnt32 (unsigned int X) { return __tzcnt_u32(X); } + +unsigned int +func_tzcnt32_2 (unsigned int X) +{ + return _tzcnt_u32(X); +} diff --git a/gcc/testsuite/gcc.target/i386/bmi-2.c b/gcc/testsuite/gcc.target/i386/bmi-2.c index 68d06a20540..6eea66aa0f6 100644 --- a/gcc/testsuite/gcc.target/i386/bmi-2.c +++ b/gcc/testsuite/gcc.target/i386/bmi-2.c @@ -2,10 +2,10 @@ /* { dg-options "-O2 -mbmi " } */ /* { dg-final { scan-assembler "andn\[^\\n]*rax" } } */ /* { dg-final { scan-assembler-times "bextr\[ \\t]+\[^\\n]*rax" 2 } } */ -/* { dg-final { scan-assembler "blsi\[^\\n]*rax" } } */ -/* { dg-final { scan-assembler "blsmsk\[^\\n]*rax" } } */ -/* { dg-final { scan-assembler "blsr\[^\\n]*rax" } } */ -/* { dg-final { scan-assembler "tzcntq\[^\\n]*rax" } } */ +/* { dg-final { scan-assembler-times "blsi\[^\\n]*rax" 2 } } */ +/* { dg-final { scan-assembler-times "blsmsk\[^\\n]*rax" 2 } } */ +/* { dg-final { scan-assembler-times "blsr\[^\\n]*rax" 2 } } */ +/* { dg-final { scan-assembler-times "tzcntq\[^\\n]*rax" 2 } } */ #include <x86intrin.h> @@ -36,19 +36,43 @@ func_blsi64 (unsigned long long X) } unsigned long long +func_blsi64_2 (unsigned long long X) +{ + return _blsi_u64 (X); +} + +unsigned long long func_blsmsk64 (unsigned long long X) { return __blsmsk_u64 (X); } unsigned long long +func_blsmsk64_2 (unsigned long long X) +{ + return _blsmsk_u64 (X); +} + +unsigned long long func_blsr64 (unsigned long long X) { return __blsr_u64 (X); } unsigned long long +func_blsr64_2 (unsigned long long X) +{ + return _blsr_u64 (X); +} + +unsigned long long func_tzcnt64 (unsigned long long X) { return __tzcnt_u64 (X); } + +unsigned long long +func_tzcnt64_2 (unsigned long long X) +{ + return _tzcnt_u64 (X); +} |