diff options
| author | mzakirov <mzakirov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-07-11 09:02:39 +0000 |
|---|---|---|
| committer | Dongkyun, Son <dongkyun.s@samsung.com> | 2015-12-08 12:17:38 +0900 |
| commit | 96f220dc2e300ae12d4da6a7568f9430c29b7ed1 (patch) | |
| tree | cb55bc2e2e8ddd5d1969fcc44b797b8625610b2c /gcc | |
| parent | bb8beded7fc57f30ae79de2aa77eb88b6bb748dc (diff) | |
| download | linaro-gcc-96f220dc2e300ae12d4da6a7568f9430c29b7ed1.tar.gz linaro-gcc-96f220dc2e300ae12d4da6a7568f9430c29b7ed1.tar.bz2 linaro-gcc-96f220dc2e300ae12d4da6a7568f9430c29b7ed1.zip | |
gcc/ 2014-07-11 Marat Zakirov <m.zakirov@samsung.com>
PR target/61561
* config/arm/arm.md (*movhi_insn_arch4): Handle stack pointer.
(*movhi_bytes): Likewise.
(*arm_movqi_insn): Likewise.
gcc/testsuite/
2014-07-11 Marat Zakirov <m.zakirov@samsung.com>
PR target/61561
* gcc.dg/pr61561.c: New test.
Change-Id: I977cff643e5fa4b119a3c662510bdf7664d8a2e6
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@212450 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/arm/arm.md | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/pr61561.c | 15 |
2 files changed, 18 insertions, 3 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b0551ee8ed5..6a0760f5449 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -6988,7 +6988,7 @@ ;; Pattern to recognize insn generated default case above (define_insn "*movhi_insn_arch4" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r") - (match_operand:HI 1 "general_operand" "rI,K,n,r,mi"))] + (match_operand:HI 1 "general_operand" "rIk,K,n,r,mi"))] "TARGET_ARM && arm_arch4 && (register_operand (operands[0], HImode) @@ -7015,7 +7015,7 @@ (define_insn "*movhi_bytes" [(set (match_operand:HI 0 "s_register_operand" "=r,r,r") - (match_operand:HI 1 "arm_rhs_operand" "I,r,K"))] + (match_operand:HI 1 "arm_rhs_operand" "I,rk,K"))] "TARGET_ARM" "@ mov%?\\t%0, %1\\t%@ movhi @@ -7147,7 +7147,7 @@ (define_insn "*arm_movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,l,r,l,Uu,r,m") - (match_operand:QI 1 "general_operand" "r,r,I,Py,K,Uu,l,m,r"))] + (match_operand:QI 1 "general_operand" "rk,rk,I,Py,K,Uu,l,m,r"))] "TARGET_32BIT && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" diff --git a/gcc/testsuite/gcc.dg/pr61561.c b/gcc/testsuite/gcc.dg/pr61561.c new file mode 100644 index 00000000000..1512f20e3d0 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr61561.c @@ -0,0 +1,15 @@ +/* PR c/61561. */ +/* { dg-do assemble } */ +/* { dg-options " -w -O2" } */ + +int dummy (int a); + +char a; +short b; + +void mmm (void) +{ + char dyn[dummy (3)]; + a = (char)&dyn[0]; + b = (short)&dyn[0]; +} |