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| author | Christophe Lyon <christophe.lyon@linaro.org> | 2017-01-24 20:44:04 +0000 |
|---|---|---|
| committer | Yvan Roux <yvan.roux@linaro.org> | 2017-01-30 13:32:43 +0000 |
| commit | 0ba52ae4f96d71f9640697427cc723f25d713c8e (patch) | |
| tree | d68f9bff22e219516355f5f8443385bc0d9b8cff /gcc | |
| parent | 79a3b2270beb68a6863d7c76017757fab4a4e27f (diff) | |
| download | linaro-gcc-0ba52ae4f96d71f9640697427cc723f25d713c8e.tar.gz linaro-gcc-0ba52ae4f96d71f9640697427cc723f25d713c8e.tar.bz2 linaro-gcc-0ba52ae4f96d71f9640697427cc723f25d713c8e.zip | |
gcc/
Backport from trunk r243755.
2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.md: New define_split above insv<mode>.
gcc/testsuite/
Backport from trunk r243755.
2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/ubfx_lsr_1.c: New test.
gcc/
Backport from trunk r243756.
2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.md: New define_split above bswap<mode>2.
gcc/testsuite/
Backport from trunk r243756.
2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/ubfiz_lsl_1.c: New test.
Change-Id: Ic891f120d65097d78a92ce5133c25d0710cf7405
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 38 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c | 13 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/ubfx_lsr_1.c | 14 |
3 files changed, 65 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 53a1ed915a8..548ca09046d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4299,6 +4299,26 @@ [(set_attr "type" "bfx")] ) +;; When the bit position and width add up to 32 we can use a W-reg LSR +;; instruction taking advantage of the implicit zero-extension of the X-reg. +(define_split + [(set (match_operand:DI 0 "register_operand") + (zero_extract:DI (match_operand:DI 1 "register_operand") + (match_operand 2 + "aarch64_simd_shift_imm_offset_di") + (match_operand 3 + "aarch64_simd_shift_imm_di")))] + "IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]), 1, + GET_MODE_BITSIZE (DImode) - 1) + && (INTVAL (operands[2]) + INTVAL (operands[3])) + == GET_MODE_BITSIZE (SImode)" + [(set (match_dup 0) + (zero_extend:DI (lshiftrt:SI (match_dup 4) (match_dup 3))))] + { + operands[4] = gen_lowpart (SImode, operands[1]); + } +) + ;; Bitfield Insert (insv) (define_expand "insv<mode>" [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand") @@ -4393,6 +4413,24 @@ [(set_attr "type" "bfx")] ) +;; When the bit position and width of the equivalent extraction add up to 32 +;; we can use a W-reg LSL instruction taking advantage of the implicit +;; zero-extension of the X-reg. +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI (ashift:DI (match_operand:DI 1 "register_operand") + (match_operand 2 "const_int_operand")) + (match_operand 3 "const_int_operand")))] + "aarch64_mask_and_shift_for_ubfiz_p (DImode, operands[3], operands[2]) + && (INTVAL (operands[2]) + popcount_hwi (INTVAL (operands[3]))) + == GET_MODE_BITSIZE (SImode)" + [(set (match_dup 0) + (zero_extend:DI (ashift:SI (match_dup 4) (match_dup 2))))] + { + operands[4] = gen_lowpart (SImode, operands[1]); + } +) + (define_insn "bswap<mode>2" [(set (match_operand:GPI 0 "register_operand" "=r") (bswap:GPI (match_operand:GPI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c b/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c new file mode 100644 index 00000000000..d3fd3f234f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* Check that an X-reg UBFIZ can be simplified into a W-reg LSL. */ + +long long +f2 (long long x) +{ + return (x << 5) & 0xffffffff; +} + +/* { dg-final { scan-assembler "lsl\tw" } } */ +/* { dg-final { scan-assembler-not "ubfiz\tx" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ubfx_lsr_1.c b/gcc/testsuite/gcc.target/aarch64/ubfx_lsr_1.c new file mode 100644 index 00000000000..f6f72b074e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ubfx_lsr_1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* Check that an X-reg UBFX can be simplified into a W-reg LSR. */ + +int +f (unsigned long long x) +{ + x = (x >> 24) & 255; + return x + 1; +} + +/* { dg-final { scan-assembler "lsr\tw" } } */ +/* { dg-final { scan-assembler-not "ubfx\tx" } } */ |