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author | brendan <brendan@138bc75d-0d04-0410-961f-82ee72b054a4> | 1997-06-06 02:20:14 +0000 |
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committer | brendan <brendan@138bc75d-0d04-0410-961f-82ee72b054a4> | 1997-06-06 02:20:14 +0000 |
commit | eaa3d982324dd200aca5d21040ae4bd1a92d076b (patch) | |
tree | d32ce468cc1c82a957b07c5722d70e1e2c91f971 /gcc/config/i960/vx960-coff.h | |
parent | 7d856d9b86899e36a84a5685ebf95c17abd72cc1 (diff) | |
download | linaro-gcc-eaa3d982324dd200aca5d21040ae4bd1a92d076b.tar.gz linaro-gcc-eaa3d982324dd200aca5d21040ae4bd1a92d076b.tar.bz2 linaro-gcc-eaa3d982324dd200aca5d21040ae4bd1a92d076b.zip |
* i960/vx960-coff.h (CPP_SPEC): Always define CPU, even if they
use -ansi; the VxWorks headers assume it's always present.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@14158 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/i960/vx960-coff.h')
-rw-r--r-- | gcc/config/i960/vx960-coff.h | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/gcc/config/i960/vx960-coff.h b/gcc/config/i960/vx960-coff.h index 3e12bbe536c..b2e93fb9976 100644 --- a/gcc/config/i960/vx960-coff.h +++ b/gcc/config/i960/vx960-coff.h @@ -35,7 +35,10 @@ Boston, MA 02111-1307, USA. */ #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Dvxworks -Acpu(i960) -Amachine(i960)" /* The VxWorks header files expect the compiler to define CPU to a - magic number. */ + magic number. Note that we define CPU here even if the user + has specified -ansi. This violates user namespace, but the VxWorks + headers, and potentially user code, all explicitly rely upon the + definition of CPU in order to get the proper processor information. */ #undef CPP_SPEC #define CPP_SPEC "%{mic*:-D__i960\ @@ -44,16 +47,16 @@ Boston, MA 02111-1307, USA. */ %{mmc:-D__i960MC}\ %{mca:-D__i960CA}%{mcc:-D__i960CC}\ %{mcf:-D__i960CF}}\ - %{mka:-D__i960KA__ -D__i960_KA__ %{!ansi:-DCPU=I960KA}}\ - %{mkb:-D__i960KB__ -D__i960_KB__ %{!ansi:-DCPU=I960KB}}\ + %{mka:-D__i960KA__ -D__i960_KA__ -DCPU=I960KA}\ + %{mkb:-D__i960KB__ -D__i960_KB__ -DCPU=I960KB}\ %{msa:-D__i960SA__ -D__i960_SA__}\ %{msb:-D__i960SB__ -D__i960_SB__}\ %{mmc:-D__i960MC__ -D__i960_MC__}\ - %{mca:-D__i960CA__ -D__i960_CA__ %{!ansi:-DCPU=I960CA}}\ + %{mca:-D__i960CA__ -D__i960_CA__ -DCPU=I960CA}\ %{mcc:-D__i960CC__ -D__i960_CC__}\ %{mcf:-D__i960CF__ -D__i960_CF__}\ %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\ - %{!mcc:%{!mcf:-D__i960_CA -D__i960CA__ %{!ansi:-DCPU=I960CA}\ + %{!mcc:%{!mcf:-D__i960_CA -D__i960CA__ -DCPU=I960CA\ %{mic*:-D__i960CA}}}}}}}}}" /* Default to -mca. */ |