diff options
| author | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2003-03-23 01:36:22 +0000 |
|---|---|---|
| committer | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2003-03-23 01:36:22 +0000 |
| commit | 4e30d7e6201f4bd94e77b2c5fde23ca8e97af133 (patch) | |
| tree | 324ada7c1baba88f8948d16ca4ff31c12b710017 /boehm-gc | |
| parent | 82d63f7c3bed3efcf5ec02e6777e67cbd922c751 (diff) | |
| download | linaro-gcc-4e30d7e6201f4bd94e77b2c5fde23ca8e97af133.tar.gz linaro-gcc-4e30d7e6201f4bd94e77b2c5fde23ca8e97af133.tar.bz2 linaro-gcc-4e30d7e6201f4bd94e77b2c5fde23ca8e97af133.zip | |
* include/private/gc_locks.h [IA64]: Include ia64intrin.h.
(GC_test_and_set): Use __sync_lock_test_and_set.
(GC_clear): Use volatile assignment.
(GC_compare_and_exchange): Use __sync_bool_compare_and_swap.
(GC_memory_write_barrier): Use __sync_synchronize.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@64736 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'boehm-gc')
| -rw-r--r-- | boehm-gc/ChangeLog | 8 | ||||
| -rw-r--r-- | boehm-gc/include/private/gc_locks.h | 21 |
2 files changed, 15 insertions, 14 deletions
diff --git a/boehm-gc/ChangeLog b/boehm-gc/ChangeLog index dd1d4a8888e..fc5cbe746a9 100644 --- a/boehm-gc/ChangeLog +++ b/boehm-gc/ChangeLog @@ -1,3 +1,11 @@ +2003-03-22 Richard Henderson <rth@redhat.com> + + * include/private/gc_locks.h [IA64]: Include ia64intrin.h. + (GC_test_and_set): Use __sync_lock_test_and_set. + (GC_clear): Use volatile assignment. + (GC_compare_and_exchange): Use __sync_bool_compare_and_swap. + (GC_memory_write_barrier): Use __sync_synchronize. + 2003-03-12 Andreas Schwab <schwab@suse.de> * configure.in: Avoid trailing /. in toolexeclibdir. diff --git a/boehm-gc/include/private/gc_locks.h b/boehm-gc/include/private/gc_locks.h index 33101f8c2d0..9b91ada917a 100644 --- a/boehm-gc/include/private/gc_locks.h +++ b/boehm-gc/include/private/gc_locks.h @@ -100,17 +100,13 @@ # define GC_TEST_AND_SET_DEFINED # endif # if defined(IA64) +# include <ia64intrin.h> inline static int GC_test_and_set(volatile unsigned int *addr) { - long oldval, n = 1; - __asm__ __volatile__("xchg4 %0=%1,%2" - : "=r"(oldval), "=m"(*addr) - : "r"(n), "1"(*addr) : "memory"); - return oldval; + return __sync_lock_test_and_set(addr, 1); } # define GC_TEST_AND_SET_DEFINED - /* Should this handle post-increment addressing?? */ inline static void GC_clear(volatile unsigned int *addr) { - __asm__ __volatile__("st4.rel %0=r0" : "=m" (*addr) : : "memory"); + *addr = 0; } # define GC_CLEAR_DEFINED # endif @@ -326,20 +322,17 @@ # if defined(IA64) # if !defined(GENERIC_COMPARE_AND_SWAP) inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr, - GC_word old, GC_word new_val) + GC_word old, + GC_word new_val) { - unsigned long oldval; - __asm__ __volatile__("mov ar.ccv=%4 ;; cmpxchg8.rel %0=%1,%2,ar.ccv" - : "=r"(oldval), "=m"(*addr) - : "r"(new_val), "1"(*addr), "r"(old) : "memory"); - return (oldval == old); + return __sync_bool_compare_and_swap (addr, old, new_val); } # endif /* !GENERIC_COMPARE_AND_SWAP */ # if 0 /* Shouldn't be needed; we use volatile stores instead. */ inline static void GC_memory_write_barrier() { - __asm__ __volatile__("mf" : : : "memory"); + __sync_synchronize (); } # endif /* 0 */ # endif /* IA64 */ |