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2013-12-03H.264: Support Constrained Baseline profile instead of Baseline profileXiang, Haihao1-1/+1
GENx doesn't support FMO/ASO, so remove the support of Baseline profile for conformance testing. In addition, add the support for Constrained Baseline profile. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-12-03dec/mpeg2: ignore slices which aren't in raster scan order on SNBXiang, Haihao1-0/+41
Sometimes codec layer incorrectly fills slice parameters due to the corrupted video Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71276 Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-04-03Merge branch 'master' into stagingXiang, Haihao1-9/+12
Conflicts: NEWS configure.ac src/Makefile.am src/gen6_mfc.c src/gen6_mfd.c src/gen6_vme.c src/gen6_vme.h src/gen75_mfc.c src/gen75_mfd.c src/gen75_vme.c src/gen75_vpp_vebox.c src/gen75_vpp_vebox.h src/gen7_mfd.c src/i965_avc_bsd.c src/i965_decoder.h src/i965_decoder_utils.c src/i965_defines.h src/i965_drv_video.c src/i965_drv_video.h src/i965_encoder.c src/i965_encoder.h src/i965_output_dri.c src/i965_post_processing.c src/i965_post_processing.h src/i965_render.c src/i965_structs.h src/intel_driver.c src/object_heap.c src/shaders/post_processing/Common/AYUV_Load_16x8.asm src/shaders/post_processing/Common/AYUV_Load_16x8.inc src/shaders/post_processing/Common/Init_All_Regs.asm src/shaders/post_processing/Makefile.am src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc src/shaders/post_processing/gen5_6/Makefile.am src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b src/shaders/post_processing/gen7/EOT.g4a src/shaders/post_processing/gen7/Makefile.am src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a src/shaders/post_processing/gen7/Save_AVS_NV12.g4a src/shaders/post_processing/gen7/Save_AVS_PA.g4a src/shaders/post_processing/gen7/Save_AVS_PL3.g4a src/shaders/post_processing/gen7/Save_AVS_RGB.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a src/shaders/post_processing/gen7/Set_Layer_0.g4a src/shaders/post_processing/gen7/VP_Setup.g4a src/shaders/vme/Makefile.am src/shaders/vme/inter_frame_haswell.asm src/shaders/vme/inter_frame_haswell.g75b src/shaders/vme/intra_frame_haswell.asm src/shaders/vme/intra_frame_haswell.g75b src/shaders/vme/vme75.inc src/shaders/vme/vme7_mpeg2.inc
2013-03-15Decoder: directly use surface object for decodingXiang, Haihao1-48/+211
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-03-15Decoder: Verify picture parameter before set up pipeline for decodingXiang, Haihao1-2/+139
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-03-15Decoder: check whether the surface for decoding output is validXiang, Haihao1-0/+74
In addition, uses the corresponding surface object directly. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-03-15Silence a bunch of warningsXiang, Haihao1-1/+1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-01-04naive fix in avc_get_first_mb_bit_offset_with_epbTobias Jakobi1-4/+4
Bugzilla:://bugs.freedesktop.org/show_bug.cgi?id=58875 Signed-off-by: Tobias Jakobi <liquid.acid@gmx.net>
2012-12-28h264: fix first macroblock bit offset calculation (ILK, SNB, IVB).Gwenole Beauchesne1-0/+55
Fix and simplify the scan for emulation_prevention_bytes, thus avoiding a read beyond the end of the slice data buffer. Besides, if slice_header() bytes are needed, use dri_bo_get_subdata() instead. HW specific changes: - SNB: make the HW skip the emulation prevention bytes itself. - IVB: fix MFD_AVC_BSD_OBJECT to report the actual slice data buffer size. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> (cherry picked from commit 9b7863bf49dcf8bf1de9b45ce4e986dfd1cca418)
2012-11-05Fix build and remaining compilation warnings.Gwenole Beauchesne1-3/+1
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-03-30mpeg2: propagate reference surfaces to other slots.Gwenole Beauchesne1-2/+6
Fill in remaining reference surfaces as recommanded in HW specs. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-03-30mpeg2: propagate reference surfaces to other slots.Gwenole Beauchesne1-2/+6
Fill in remaining reference surfaces as recommanded in HW specs. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-03-29mpeg2: fix construction of reference frames list (SNB, IVB).Gwenole Beauchesne1-0/+86
Fix construction of reference frames list for interlaced streams. In this case, the array is indexed by frame store ID >> 1 where bit 0 of frame store ID represents top (0) or bottom (1) field. Besides, current render target can also be used as a reference while decoding the second field. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> (cherry picked from commit 14f70559b516030d141cce09db54cf49d11df9b2)
2012-03-29mpeg2: fix incorrect slice_vertical_position from codec layers.Gwenole Beauchesne1-0/+41
Correctly emit slice_vertical_position, as per the definition from the bitstream, to the HW decoder (MFD_MPEG2_BSD_OBJECT). Add workaround for players that have not fixed their usage of slice_vertical_position. That field shall represent the slice vertical position as it comes from the bitstream. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> (cherry picked from commit 298dc939835e3080c9330b4e52e8dfac25bf3060) Conflicts: NEWS
2012-03-18mpeg2: fix construction of reference frames list (SNB, IVB).Gwenole Beauchesne1-0/+86
Fix construction of reference frames list for interlaced streams. In this case, the array is indexed by frame store ID >> 1 where bit 0 of frame store ID represents top (0) or bottom (1) field. Besides, current render target can also be used as a reference while decoding the second field. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-03-18mpeg2: fix incorrect slice_vertical_position from codec layers.Gwenole Beauchesne1-0/+41
Correctly emit slice_vertical_position, as per the definition from the bitstream, to the HW decoder (MFD_MPEG2_BSD_OBJECT). Add workaround for players that have not fixed their usage of slice_vertical_position. That field shall represent the slice vertical position as it comes from the bitstream. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-03-14h264: fix max header size calculation with EPB.Gwenole Beauchesne1-1/+1
... aka fix wrong patch applied. For the records, considering header size without EPB is N, then the max header size with EPB is N * 3/2. However, it's not possible to reach this value since that would mean that slice_header() only contained zeroes. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-03-14h264: fix scan for bit offset to macroblock.Gwenole Beauchesne1-7/+8
Handle two indices in parallel, one relative to the bitstream with EPB, and the other without EPB. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-03-02h264: fix first macroblock bit offset calculation (ILK, SNB, IVB).Gwenole Beauchesne1-0/+55
Fix and simplify the scan for emulation_prevention_bytes, thus avoiding a read beyond the end of the slice data buffer. Besides, if slice_header() bytes are needed, use dri_bo_get_subdata() instead. HW specific changes: - SNB: make the HW skip the emulation prevention bytes itself. - IVB: fix MFD_AVC_BSD_OBJECT to report the actual slice data buffer size. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-02-14h264: always submit MFX_QM_STATE for flat scaling lists (IVB).Gwenole Beauchesne1-0/+12
If codec layer does not provide a VAIQMatrixBufferH264, this means flat scaling lists shall be used. The MFX_QM_STATE command still has to be submitted since IVB+ does not have a means to use HW generated scaling lists. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-02-01h264: fix and simplify REF_IDX_STATE (ILK, SNB, IVB).Gwenole Beauchesne1-0/+130
Original code was parsing RefPicList0/1 over what is actually available and filled in, i.e. wrt. num_ref_idx_l0/1_minus1 + 1. Besides, bit 5 of Reference List Entry set to 1 means a frame, not a field. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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