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2014-09-02H264_Encoding: Fix the incorrect Qp setting under CBR when slice_header is ↵Zhao Yakui1-4/+12
passed Fix the issue in https://bugs.freedesktop.org/show_bug.cgi?id=83143 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Tested-by: Sreerenj Balachandran <sreerenj.balachandran@intel.com> (cherry picked from commit eca8e0065e3a04156e0817d3a5ac14f4df39d603) Conflicts: src/gen6_mfc.c src/gen8_mfc.c
2014-06-16H264_encoding: Don't update the slice qp for CBR mode when finding packed ↵Zhao, Yakui1-2/+4
slice_header data Otherwise the slice qp is inconsistent and the encoding is incorrect. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 897527c30435202927e6cd05cd5189a710d02c91)
2014-06-16H264_Encoding: Add the support of packed slice header to be flexibleZhao, Yakui1-30/+0
Under some encoding scenario, the user hopes to generate the packed slice header data by themself and then the driver can insert the passed slice header packed data into the coded clip. 1.The VA_ENC_PACKED_HEADER_SLICE flag is exported and it is treated as optional. This is to say: if packed slice header data is passed, it will be inserted directly. If no packed slice header data is passed, the driver will help to generate it. 2.Another restriction is that the packed slice header data is inserted after the packed rawdata for one slice. That is to say: If it needs to insert the packed rawdata and slice header data, the packed rawdata will be inserted firstly(This is handled by the driver). Signed-off-by: Zhao, Yakui <yakui.zhao@intel.com> (cherry picked from commit 00111e8a8bfa67b971419b72577eaa1b9f47bc34) Conflicts: src/gen75_mfc.c src/gen8_mfc.c
2014-06-16H264_encoding: Add the support of inserting the packed raw data passed from userZhao, Yakui1-2/+4
Under some encoding scenario, the user-space application hopes that the driver can insert the passed packed rawdata into the coded clip. This is to allow the insertion of packed rawdata passed from user. As the position of packed rawdata is related with the slice. So the following restrictions are added: 1. the packed rawdata header type/data should be paired. 2. the packed rawdata data is inserted by following the passed order 3. the packed rawdata header type/data is split by using VAEncSliceParameterBuffer. That is to say: The packed rawdata for slice 0 should be passed before the first VAEncSliceParameterBuffer. After one VAEncSliceParameterBuffer is parsed, the subseuquent packed rawdata is for another new slice. The subsequent packed rawdata after the last VAEncSliceParameterBuffer is ignored. 4. it does not change the rule for the packed data of SPS/PPS/MISC type. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 974597ef64dc9a283d4787e1484a75d1610414f4) Conflicts: src/gen75_mfc.c src/gen8_mfc.c
2014-06-16encoder: MVC: Add support for MVC profilesLi Xiaowei1-4/+9
This is a part of bd630edd844b88ea543a027654db296ff7da16cd on staging Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2014-04-23Use the VA_FOURCC_ABCD constant to replace the VA_FOURCC(A,B,C,D)Zhao Yakui1-1/+1
This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D). Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit acea969011bceee36a57fe2c0e4ee96c0c5e79c7)
2014-02-27Update the MFX_AVC_IMAGE_STATE to follow the specZhao Yakui1-1/+1
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Handle the aux_batchbuffer correctly for H264 encoding on HaswellZhao Yakui1-1/+3
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Avoid the duplicated macro-definition of surface sizeZhao Yakui1-0/+4
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2013-12-03H.264: Support Constrained Baseline profile instead of Baseline profileXiang, Haihao1-1/+1
GENx doesn't support FMO/ASO, so remove the support of Baseline profile for conformance testing. In addition, add the support for Constrained Baseline profile. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-11-13Remove the unused variable to avoid the warningZhao Yakui1-4/+1
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 0d37a309bd99f6bded4df922d0ece22bf3bb1757)
2013-11-13Use GPU to construct MFX command buffer for H264 encoding on HaswellZhao Yakui1-157/+113
This is to optimze the performance of h264 encoding. The GPU can accelerate the construction of MFX command buffer for H264 encoding. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 87bc38d4300212dea51b5635f184aa1ae37fa71c)
2013-11-13Encoding reuses aux_batchbuffer instead of allocating another new bufferZhao Yakui1-11/+7
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 052ce2930cd4661b7ce62902e6553eec0e2db9f1)
2013-11-13Calculate the required space of batch buffer to avoid buffer overflow in ↵Zhao Yakui1-1/+6
encoding The required size is based on the number of macroblocks and slice parameter. Then it can avoid that too large buffer is allocated or possible overflow. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 8acdfd023e50af37a5642e2517683c34accd78b0)
2013-11-13Follow the input Picture/Slice parameters to generate slice header/dataXiang, Haihao1-11/+21
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit f5a694e64d0163178c28dc25d9a3e7b9b1b5d162)
2013-11-13Pass the reference frame index in List0/1 into the PAK commandXiang, Haihao1-2/+3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 68380a7f141bedcc0f6fbbbcee2f5e42b6ade0e0)
2013-11-13Indent the code of encodingXiang, Haihao1-262/+262
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 6ad68f55e9ba49af541a5e4d86a305bbd0f22d63)
2013-09-06Optimize quantization rounding precision for MPEG2 encoding on haswellZhao Yakui1-1/+7
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 24d8bf31c8aeb326bc8b33c1ac9700ec1d169666)
2013-09-06Enable the Intra-prediction for MPEG2 P-B frameZhao Yakui1-1/+20
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit c074d4d61ad931d044fbe0836a45c49768090b4b)
2013-09-06Use the right wight/height to initialize the internal buffers for MPEG-2 ↵Xiang, Haihao1-3/+15
encoding Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 3ecbff585af918d96959ce791eec29be25360d91)
2013-09-06Cleanup profile tracking in encoderXiang, Haihao1-1/+1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit edd25a94e92b9cec23594dc978691506a1c8cfab)
2013-09-06Rename the macrosXiang, Haihao1-1/+1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 3ab97be8db1b8e55d0d5b95f577863416a87c6ff)
2013-05-09PAK encoding uses the reference list parsed from slice_param instead of ↵Zhao Yakui1-1/+1
hacked DPB Of course it still can work if the slice_param doesn't contain the valid REfPicList0/1(Hacked DPB mode). This is to be compatible with the older version of avcenc tool. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2013-05-09Unify the AVC ref frame index setting on Snb/Ivy/HSWZhao Yakui1-26/+1
This is to remove the duplicated code. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2013-04-03Merge branch 'master' into stagingXiang, Haihao1-5/+4
Conflicts: NEWS configure.ac src/Makefile.am src/gen6_mfc.c src/gen6_mfd.c src/gen6_vme.c src/gen6_vme.h src/gen75_mfc.c src/gen75_mfd.c src/gen75_vme.c src/gen75_vpp_vebox.c src/gen75_vpp_vebox.h src/gen7_mfd.c src/i965_avc_bsd.c src/i965_decoder.h src/i965_decoder_utils.c src/i965_defines.h src/i965_drv_video.c src/i965_drv_video.h src/i965_encoder.c src/i965_encoder.h src/i965_output_dri.c src/i965_post_processing.c src/i965_post_processing.h src/i965_render.c src/i965_structs.h src/intel_driver.c src/object_heap.c src/shaders/post_processing/Common/AYUV_Load_16x8.asm src/shaders/post_processing/Common/AYUV_Load_16x8.inc src/shaders/post_processing/Common/Init_All_Regs.asm src/shaders/post_processing/Makefile.am src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc src/shaders/post_processing/gen5_6/Makefile.am src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b src/shaders/post_processing/gen7/EOT.g4a src/shaders/post_processing/gen7/Makefile.am src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a src/shaders/post_processing/gen7/Save_AVS_NV12.g4a src/shaders/post_processing/gen7/Save_AVS_PA.g4a src/shaders/post_processing/gen7/Save_AVS_PL3.g4a src/shaders/post_processing/gen7/Save_AVS_RGB.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a src/shaders/post_processing/gen7/Set_Layer_0.g4a src/shaders/post_processing/gen7/VP_Setup.g4a src/shaders/vme/Makefile.am src/shaders/vme/inter_frame_haswell.asm src/shaders/vme/inter_frame_haswell.g75b src/shaders/vme/intra_frame_haswell.asm src/shaders/vme/intra_frame_haswell.g75b src/shaders/vme/vme75.inc src/shaders/vme/vme7_mpeg2.inc
2013-03-15Encoder: directly use the objects for the reference picturesXiang, Haihao1-4/+2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-03-15Encoder: directly use the objects for the reconstructed picture and coded bufferXiang, Haihao1-4/+2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-03-15Encoder: directly use the surface object of the input surfaceXiang, Haihao1-2/+1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-03-15Silence a bunch of warningsXiang, Haihao1-1/+1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-03-15Avoid potential buffer overflow issueXiang, Haihao1-20/+13
Warning if the slice type is wrong for encoding Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-01-30Correct the mv offset for mpeg2 encoding on HSWstaging-20130205Li Xiaowei1-5/+5
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
2013-01-17apply new mv offset for mpeg2 encoding on HSWLi Xiaowei1-11/+5
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
2013-01-17Add the bidirectional MV prediction for B-frame on HaswellZhao Yakui1-3/+12
Now the B-frame only supports the forward prediction. In order to get the better prediction result, the bidirection prediction is added for B-frame. At the same time the MV prediction is also added. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2013-01-17Remove the preprocessor redefinitions for H264 and MPEG2 on HaswellZhao Yakui1-9/+9
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2013-01-17Discard the intermediate result during VME prediction on haswellZhao Yakui1-3/+3
There is no functional change. It is only to avoid writing the intermediate result of VME prediction. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-12-14Fix Motion VectorXiang, Haihao1-23/+42
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-12-14MPEG-2 encoding: Use pre deblocking output for reconstructed picture.Xiang, Haihao1-2/+2
This avoids OLDB enabling for MPEG-2 Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-12-14Follow the vme output to configure PAK commandXiang, Haihao1-12/+48
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-12-14PAK command for inter macroblockXiang, Haihao1-1/+76
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-12-14Update coded_block_patternXiang, Haihao1-1/+1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-12-14Change the max sizeXiang, Haihao1-1/+1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-12-14Update QM/FQM matrices for MPEG-2 encodingXiang, Haihao1-18/+44
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-12-14No emulation bytes for MPEG-2Xiang, Haihao1-3/+3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-12-14Internal flag for the coded bufferXiang, Haihao1-16/+16
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-12-14rename I965_CODEDBUFFER_SIZEXiang, Haihao1-1/+1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-12-14Insert some redunrant data around a sliceXiang, Haihao1-27/+38
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-12-14Setup MFC pipeline for MPEG-2 encoding on HaswellXiang, Haihao1-2/+561
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-12-14Feed MFC PAK with correct MV of VME output on haswellZhao Yakui1-0/+37
This is helpful to improve the video compress rate of H264 encoding. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-12-14Add the support of the chroma intra prediction on HaswellZhao Yakui1-1/+1
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-12-14Fix the corrupted macroblock for AVC encoding on HSWZhao Yakui1-0/+1
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
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