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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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To build the code, a new version of VA-API is needed, so
update the dependency on VA-API as well
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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The new version of intel-gen4asm is required to build shaders
for BDW
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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This is the first VPP shader for BDW,which is used to do the
NV12 scaling conversion.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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This fixes https://bugs.freedesktop.org/show_bug.cgi?id=66258
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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libdrm 2.4.45 is required to support VEBOX on HSW
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Conflicts:
NEWS
configure.ac
src/Makefile.am
src/gen6_mfc.c
src/gen6_mfd.c
src/gen6_vme.c
src/gen6_vme.h
src/gen75_mfc.c
src/gen75_mfd.c
src/gen75_vme.c
src/gen75_vpp_vebox.c
src/gen75_vpp_vebox.h
src/gen7_mfd.c
src/i965_avc_bsd.c
src/i965_decoder.h
src/i965_decoder_utils.c
src/i965_defines.h
src/i965_drv_video.c
src/i965_drv_video.h
src/i965_encoder.c
src/i965_encoder.h
src/i965_output_dri.c
src/i965_post_processing.c
src/i965_post_processing.h
src/i965_render.c
src/i965_structs.h
src/intel_driver.c
src/object_heap.c
src/shaders/post_processing/Common/AYUV_Load_16x8.asm
src/shaders/post_processing/Common/AYUV_Load_16x8.inc
src/shaders/post_processing/Common/Init_All_Regs.asm
src/shaders/post_processing/Makefile.am
src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm
src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc
src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm
src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm
src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm
src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc
src/shaders/post_processing/gen5_6/Makefile.am
src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b
src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b
src/shaders/post_processing/gen7/EOT.g4a
src/shaders/post_processing/gen7/Makefile.am
src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/Save_AVS_NV12.g4a
src/shaders/post_processing/gen7/Save_AVS_PA.g4a
src/shaders/post_processing/gen7/Save_AVS_PL3.g4a
src/shaders/post_processing/gen7/Save_AVS_RGB.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a
src/shaders/post_processing/gen7/Set_Layer_0.g4a
src/shaders/post_processing/gen7/VP_Setup.g4a
src/shaders/vme/Makefile.am
src/shaders/vme/inter_frame_haswell.asm
src/shaders/vme/inter_frame_haswell.g75b
src/shaders/vme/intra_frame_haswell.asm
src/shaders/vme/intra_frame_haswell.g75b
src/shaders/vme/vme75.inc
src/shaders/vme/vme7_mpeg2.inc
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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error: 'AM_CONFIG_HEADER': this macro is obsolete.
You should use the 'AC_CONFIG_HEADERS' macro instead.
warning: 'INCLUDES' is the old name for 'AM_CPPFLAGS' (or '*_CPPFLAGS')
Added NOCONFIGURE check to autogen.sh
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Signed-off-by: Adrian Marius Negreanu <adrian.m.negreanu@intel.com>
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Build broke when trying to compile with expressive debug CFLAGS (-g3).
This was root-caused to the lack of the "-lm" linker flag. By adding a
simple autoconf check we ensure that libm is linked.
More specifically, recent VEBOX changes depend on cos() and sin() math
functions.
Signed-off-by: Joe Konno <joe.konno@intel.com>
(cherry picked from commit eb39abb70886d9277cf7d5114125cb7b22e7c362)
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Build broke when trying to compile with expressive debug CFLAGS (-g3).
This was root-caused to the lack of the "-lm" linker flag. By adding a
simple autoconf check we ensure that libm is linked.
More specifically, recent VEBOX changes depend on cos() and sin() math
functions.
Signed-off-by: Joe Konno <joe.konno@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Really fix build back to VA-API 0.32.0, and not only VA-API 0.32.1,
thus checking for VA/JPEG decode API. VA-API 0.32.0 was provided by
libva 1.0.15 and earlier version, which is still available in
Ubuntu 12.04-LTS.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Zhao Halley <halley.zhao@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Dmitry Ermilov <dmitry.ermilov@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Dmitry Ermilov <dmitry.ermilov@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Most OSVs adopted XXX-intel-driver as their shipping packages for the
Intel VA driver, with XXX = { vaapi, libva }. Adopt libva-intel-driver
from now on for upstream packages too.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit a52e577cc78abcfe5f008a9bffe08927a02908ac)
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Most OSVs adopted XXX-intel-driver as their shipping packages for the
Intel VA driver, with XXX = { vaapi, libva }. Adopt libva-intel-driver
from now on for upstream packages too.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Zhao Halley <halley.zhao@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Dmitry Ermilov <dmitry.ermilov@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Dmitry Ermilov <dmitry.ermilov@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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This reverts commit bcca7d23de29423b0d7d9954bfb21cc9bf3834f5.
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Preparatory work for some changes to be promoted from staging to master.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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