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2014-02-27Fix vp8 partition offset set errorZhao, Halley1-1/+2
Signed-off-by: Zhong Li <zhong.li@intel.com>
2014-02-27Fix vp8 p frame decode error issue.Zhong Li2-0/+57
Signed-off-by: Zhong Li <zhong.li@intel.com>
2014-02-27vp8 dec: fix when bool_coder_ctx.count is 0Zhao, Halley1-3/+14
bool_coder_ctx.count is remaining bits, hw requires used-bits-count: 8-bool_coder_ctx.count, range [0,7] update offset and partition_size[0] as well Signed-off-by: Zhao Halley <halley.zhao@intel.com>
2014-02-27vp8 dec: follows va_dec_vp8.h updateZhao, Halley1-3/+4
key_frame:0 means an intra frame bool_coder_ctx.count is the remaining bits in bool_coder_ctx.value, range[0,7) slice_data_offset/macroblock_offset update Signed-off-by: Zhao Halley <halley.zhao@intel.com>
2014-02-27Remove the unnecessary sorting to simplify the DPB buffer managementZhao Yakui1-41/+11
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Complain the warning instead of assert fault when slice picture is not found ↵Zhao Yakui1-3/+9
in DPB for decoder This is to fix the bug https://bugs.freedesktop.org/show_bug.cgi?id=72660 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27VPP: Correct return value of vpp gpe functionsLi Xiaowei1-8/+23
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
2014-02-27Remove the whitespace following trailing backslash in a Makefile.amXiang, Haihao1-2/+2
src/shaders/post_processing/gen8/Makefile.am:31: whitespace following trailing backslash src/shaders/post_processing/gen8/Makefile.am:32: whitespace following trailing backslash Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2014-02-27VPP: Enable sharpening feature on BDWLi Xiaowei4-31/+2501
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
2014-02-27VPP: Refine code for sharpening on HaswellLi Xiaowei3-95/+96
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
2014-02-27VEBOX/bdw: set downsample methodXiang, Haihao1-2/+2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2014-02-27VEBOX/bdw: DW0-DW8 are used for dndi parameters in VEBOX_DNDI_STATEXiang, Haihao1-1/+6
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2014-02-27Add one environment variable to check the benchmark of decoding/vaPutsurfaceZhao Yakui1-1/+2
The swap_buffer callback will wait for the completion of buffer swap, which will affect the benchmark test of decoding/vaPutSurface. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Render/BDW: Align each offset with 64 bytesXiang, Haihao1-21/+26
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Render/BDW: Initialize the blend_state for renderingXiang, Haihao1-2/+2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Render/HSW: Fix the bug caused by merging codeXiang, Haihao1-3/+1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2014-02-27Update the MFX_AVC_IMAGE_STATE to follow the specZhao Yakui6-8/+8
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Fix the incorrect MV upper bound setting of MFC_IND_OBJ_BASE_ADDRESS_STAE ↵Zhao Yakui1-1/+3
for encoding on gen8 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Fix the wrong VPP initialization function for Dn/DI on IvybridgeZhao Yakui1-1/+1
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Add the VPP shader of conversion between YUY2 and YUY2 on BDWZhao Yakui4-0/+298
Signed-off-by: Zhao Yakui <yakui.zhao2intel.com>
2014-02-27Use the pp_null_initialize function for the unsupported VPP on BDWZhao Yakui1-2/+2
The Dn/DI will be implemented by using VEBOX and doesn't use the VPP shader any more. So the corresponding VPP shader should use the pp_null_initialize hook function. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Fix the error for the VPP conversion of NV12->NV12 on BDWZhao Yakui1-1/+1
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Use the correct sub-context for VPP on BDW to avoid the NULL pointerZhao Yakui1-1/+1
The structure of sub-context is updated for VPP in the commit of 4faf6bf47f8e4e2fe587e3bb6a004340edd59c4c. So BDW should update the correct sub-context.Otherwise the segment fault will be triggered. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Add the support of querying the surface attributes on BDWZhao Yakui1-0/+110
Otherwise the user-space application doesn't query which surfaceformat is supported by the libva-vappi driver on BDW. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Fix the wrong pitch of surface for Video post-processing on BDWZhao Yakui1-2/+0
Now the object surface already contains the pitch after the object surface structure is reworked in the commit f886f24eaaacba9544fa5f6405b7382c686f3a1f. So it is unnecessary to calculate the pitch based on the width. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Follow the spec to make the VPP media pipeline work in 48-bit addressing modeZhao Yakui2-67/+331
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Fix the error of offset calculation for encoding on BDWZhao Yakui1-9/+14
Currently although the encoding can work well, the offset in the internal object is calculated incorrectly. So fix it to avoid the potential issue. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27VPP/bdw: Fix the initialize function used for NV12 to NV12Xiang, Haihao1-1/+1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2014-02-27Add the ring supported for bdw vpp filtersZhong Li1-4/+4
Signed-off-by: Zhong Li <zhong.li@intel.com>
2014-02-27Fix a bug of vp8 quant index calculation errorZhong Li1-1/+3
Signed-off-by: Zhong Li <zhong.li@intel.com>
2014-02-27Remove the unused function of gen7_pp_rgbx_avs_initializeZhao Yakui1-216/+0
This is not used any more after it uses the same gen7_pp_plx_avs_initialize function for RGBX input on Ivy/Haswell. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Configure VPP parameter for RGBX input so that Haswell/Ivy uses the same ↵Zhao Yakui1-2/+12
gen7_pp_plx_avs_initialize Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Update the supported render target format and pixel format for JPEG on BDWZhao Yakui1-16/+25
This is picked up from the commit a90e80fb7fde114535ab5e9be74d973117def138 on Ivy/Haswell. Otherwise the JPEG on BDW can't work as expected. Signed-off-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Add the support of color BT709/SMPTE240M for color-space conversion on BDWZhao Yakui5-103/+33
This is picked up from that on Haswell/Ivybridge. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Add the support of brightness/contrast/hue/saturation for BDW renderingZhao Yakui4-0/+76
This is picked up from the commit 04ecb6e79f4382d96eb5d4b51733049d420f592a Signed-off-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Fix the error in render shader for subpictureZhao Yakui9-16/+16
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Fix the error in render shader for BDWZhao Yakui2-16/+16
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Explicitly declare the color blend operation for subpicture on BDWZhao Yakui1-0/+1
Without this it still can work. This is only human-readable. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Fix the incorrect setting for subpicture on BDWZhao Yakui1-3/+32
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27BDW encoding reuses aux_batchbuffer instead of allocating another new bufferZhao Yakui1-12/+6
This is picked up from that on Haswell/Ivybridge. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Calculate required space of batch buffer to avoid buffer overflow in ↵Zhao Yakui1-1/+5
encoding on BDW The required size is based on the number of macroblocks and slice parameter. Then it can avoid that too large buffer is allocated or possible overflow. This is picked up from that on Haswell/Ivybridge. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Handle the aux_batchbuffer correctly for H264 encoding on HaswellZhao Yakui1-1/+3
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Follow spec to update the URB entry/size setting for encoding on Haswell/BDWZhao Yakui2-4/+4
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Rendering/bdw: fix push constant buffer for PSXiang, Haihao1-2/+2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2014-02-27BDW doesn't support H.264 Baseline profileXiang, Haihao2-3/+3
The similar fix to f765987 Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2014-02-27Follow the spec to make the 3D pipeline work in 48-bit addressing modeZhao Yakui2-80/+374
Signed-off-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27follow the spec to fill the Vertex URB entry on BDWZhao Yakui1-7/+29
Signed-off-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Add the missing 3D pipeline command for rendering on BDWZhao Yakui2-1/+74
Signed-off-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Follow the spec to restrict the max number of PS threadZhao Yakui1-7/+1
Signed-off-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Enable the Intra-prediction for MPEG2 P-B frame on BDWZhao Yakui1-1/+20
This is picked up from the implementation on Haswell/Ivybridge. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 17:34:59 +0000