diff options
33 files changed, 330 insertions, 269 deletions
@@ -1,13 +1,57 @@ -libva-intel-driver NEWS -- summary of changes. 2012-02-DD +libva-intel-driver NEWS -- summary of changes. 2013-03-19 Copyright (C) 2009-2011 Intel Corporation -Version 1.0.16 - DD.Feb.2012 -* Fix VC-1 bitplane buffer size (SNB, IVB) +Version 1.0.20 - 19.Mar.2013 +* Add support for wayland 1.0 protocol (Rob Bradford) +* Add global alpha support for subpicture +* Add support for IA88/AI88 subpicture +* Support up to 4 subpictures for each VA surface +* Update PCI IDs for Haswell CRW +* Automake 1.13 fixups (Armin K) +* Fix libva-intel-driver-1.0.19 display corruption on IVB GT1 + https://bugs.freedesktop.org/show_bug.cgi?id=57323 +* Fix decoding with FREXT02_JVC_C.264 on SNB + https://bugs.freedesktop.org/show_bug.cgi?id=57720 +* Fix H.264 decoding broken/visual errors on ILK (Tobias Jakobi) + https://bugs.freedesktop.org/show_bug.cgi?id=58875 +* Fix GPU hung with h.264 video and a resolution of 1920x816 on IVB + https://bugs.freedesktop.org/show_bug.cgi?id=59050 + +Version 1.0.19 - 09.Nov.2012 +* Add support for Haswell +* Add raw DRM support (Dmitry Ermilov) +* Add Wayland support +* Add support for display rotation attribute +* Support 4K encoding on IVB and HSW +* Drop explicit dependency on X11 and libva-x11 +* Fix VC-1 decoding when VSTRANSFORM is 0 +* Fix SIGSEGV caused by use-after-free of the bufmgr (Stéphane Marchesin) +* Fix thread safety issue (Gautam) +* Fix vaUnlockSurface() for libva trace + +Version 1.0.18 - 02.Aug.2012 +* Add JPEG decoding on Ivy Bridge +* Add support for a new Ivy Bridge chip +* Add support for vaSyncSurface() and vaQuerySurfaceStatus() (Dmitry Ermilov) +* Fix decoding of MPEG-2 videos with implicit IQ matrices +* Fix concurrent creation of VA objects (MT safety) +* Fix decoding of large resolution videos (up to 4K on IVB) + +Version 1.0.17 - 02.Apr.2012 +* Add support for IMC1/IMC3 surface formats +* Fix rendering of interlaced surfaces * Fix MPEG-2 decoding of interlaced streams (SNB, IVB) +* Fix H.264 weighted prediction indicator (SNB) +* Fix and simplify calculation of H.264 macroblock bit offset (ILK, SNB, IVB) + +Version 1.0.16 - 14.Feb.2012 +* Fix VC-1 bitplane buffer size (SNB, IVB) * Fix VC-1 motion vector modes for Ivy Bridge * Fix MFX_QM_STATE for H.264 flat scaling lists (IVB) * Fix and simplify AVC_REF_IDX_STATE setup (ILK, SNB, IVB) -* Fix and simplify first macroblock bit offset calculation (ILK, SNB, IVB) +* Fix memory leak of encoder buffers +* Fix check for internal VA surface format prior to rendering +* Add support for B43 chipset (Alexander Inyukhin) Version 1.0.15 - 28.Oct.2011 * Add auto-generated Debian packaging @@ -36,4 +36,4 @@ VC-1 D SNB+ Requirements ------------ -libva >= 1.0.14 +libva >= 1.0.16 @@ -1,3 +1,7 @@ #! /bin/sh + autoreconf -v --install -./configure "$@" + +if test -z "$NOCONFIGURE"; then + ./configure "$@" +fi diff --git a/configure.ac b/configure.ac index a9ed8d5..6efba77 100644 --- a/configure.ac +++ b/configure.ac @@ -1,7 +1,7 @@ # intel-driver package version number m4_define([intel_driver_major_version], [1]) m4_define([intel_driver_minor_version], [0]) -m4_define([intel_driver_micro_version], [16]) +m4_define([intel_driver_micro_version], [21]) m4_define([intel_driver_pre_version], [1]) m4_define([intel_driver_version], [intel_driver_major_version.intel_driver_minor_version.intel_driver_micro_version]) @@ -10,7 +10,7 @@ m4_append([intel_driver_version], intel_driver_pre_version, [.pre]) ]) # libva minimum version requirement -m4_define([libva_version], [0.34]) +m4_define([va_api_version], [0.34]) m4_define([libva_package_version], [1.2.0]) # libdrm minimum version requirement @@ -22,7 +22,7 @@ AC_INIT([intel_driver], [intel_driver_version], [haihao.xiang@intel.com], AC_CONFIG_SRCDIR([Makefile.am]) AM_INIT_AUTOMAKE([1.9 tar-ustar]) -AM_CONFIG_HEADER([src/config.h]) +AC_CONFIG_HEADERS([src/config.h]) INTEL_DRIVER_MAJOR_VERSION=intel_driver_major_version INTEL_DRIVER_MINOR_VERSION=intel_driver_minor_version @@ -76,12 +76,12 @@ PKG_CHECK_MODULES([DRM], [libdrm >= $LIBDRM_VERSION]) AC_SUBST(LIBDRM_VERSION) dnl Check for gen4asm -PKG_CHECK_MODULES(GEN4ASM, [intel-gen4asm >= 1.2], [gen4asm=yes], [gen4asm=no]) +PKG_CHECK_MODULES(GEN4ASM, [intel-gen4asm >= 1.3], [gen4asm=yes], [gen4asm=no]) AM_CONDITIONAL(HAVE_GEN4ASM, test x$gen4asm = xyes) AC_PATH_PROG([GEN4ASM], [intel-gen4asm]) dnl Check for VA-API -PKG_CHECK_MODULES(LIBVA_DEPS, [libva >= libva_version]) +PKG_CHECK_MODULES(LIBVA_DEPS, [libva >= va_api_version]) dnl Check for VA/DRM API USE_DRM="$enable_drm" diff --git a/src/Makefile.am b/src/Makefile.am index 3b020b6..3299733 100755 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -22,7 +22,7 @@ SUBDIRS = shaders -INCLUDES = \ +AM_CPPFLAGS = \ -DPTHREADS \ $(DRM_CFLAGS) \ $(LIBVA_DEPS_CFLAGS) \ @@ -55,11 +55,11 @@ source_c = \ gen7_mfc.c \ gen7_mfd.c \ gen75_mfd.c \ - gen75_vme.c \ gen75_mfc.c \ - gen75_vpp_vebox.c \ - gen75_vpp_gpe.c \ gen75_picture_process.c \ + gen75_vme.c \ + gen75_vpp_gpe.c \ + gen75_vpp_vebox.c \ i965_avc_bsd.c \ i965_avc_hw_scoreboard.c\ i965_avc_ildb.c \ @@ -87,9 +87,9 @@ source_h = \ gen6_mfd.h \ gen6_vme.h \ gen7_mfd.h \ - gen75_vpp_vebox.h \ - gen75_vpp_gpe.h \ gen75_picture_process.h \ + gen75_vpp_gpe.h \ + gen75_vpp_vebox.h \ i965_avc_bsd.h \ i965_avc_hw_scoreboard.h\ i965_avc_ildb.h \ @@ -111,9 +111,11 @@ source_h = \ intel_batchbuffer_dump.h\ intel_compiler.h \ intel_driver.h \ + intel_media.h \ intel_memman.h \ object_heap.h \ - intel_media.h \ + sysdeps.h \ + va_backend_compat.h \ $(NULL) i965_drv_video_la_LTLIBRARIES = i965_drv_video.la @@ -139,7 +141,7 @@ endif i965_output_wayland.c: $(protocol_source_h) @wayland_scanner_rules@ -DIST_SUBDIRS = wayland +DIST_SUBDIRS = $(SUBDIRS) wayland # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in config.h.in diff --git a/src/gen6_mfc.c b/src/gen6_mfc.c index bd5ebdc..81136ad 100644 --- a/src/gen6_mfc.c +++ b/src/gen6_mfc.c @@ -449,6 +449,7 @@ gen6_mfc_avc_slice_state(VADriverContextP ctx, ADVANCE_BCS_BATCH(batch); } + static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; diff --git a/src/gen6_mfd.c b/src/gen6_mfd.c index 4246709..3f696dd 100755 --- a/src/gen6_mfd.c +++ b/src/gen6_mfd.c @@ -26,14 +26,9 @@ * */ -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <assert.h> - +#include "sysdeps.h" #include "intel_batchbuffer.h" #include "intel_driver.h" - #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_decoder_utils.h" @@ -278,29 +273,6 @@ gen6_mfd_bsp_buf_base_addr_state(VADriverContextP ctx, ADVANCE_BCS_BATCH(batch); } -#if 0 -static void -gen6_mfd_aes_state(VADriverContextP ctx, - struct decode_state *decode_state, - int standard_select) -{ - /* FIXME */ -} - -static void -gen6_mfd_wait(VADriverContextP ctx, - struct decode_state *decode_state, - int standard_select, - struct gen6_mfd_context *gen6_mfd_context) -{ - struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; - - BEGIN_BCS_BATCH(batch, 1); - OUT_BCS_BATCH(batch, MFX_WAIT | (1 << 8)); - ADVANCE_BCS_BATCH(batch); -} -#endif - static void gen6_mfd_avc_img_state(VADriverContextP ctx, struct decode_state *decode_state, @@ -547,6 +519,7 @@ gen6_mfd_avc_slice_state(VADriverContextP ctx, pic_param->seq_fields.bits.mb_adaptive_frame_field_flag); int weighted_pred_idc = 0; int first_mb_in_slice = 0, first_mb_in_next_slice = 0; + unsigned int chroma_log2_weight_denom, luma_log2_weight_denom; int slice_type; if (slice_param->slice_type == SLICE_TYPE_I || @@ -560,6 +533,9 @@ gen6_mfd_avc_slice_state(VADriverContextP ctx, slice_type = SLICE_TYPE_B; } + luma_log2_weight_denom = slice_param->luma_log2_weight_denom; + chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom; + if (slice_type == SLICE_TYPE_I) { assert(slice_param->num_ref_idx_l0_active_minus1 == 0); assert(slice_param->num_ref_idx_l1_active_minus1 == 0); @@ -573,7 +549,13 @@ gen6_mfd_avc_slice_state(VADriverContextP ctx, } else { num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1; - weighted_pred_idc = (pic_param->pic_fields.bits.weighted_bipred_idc == 1); + weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc; + + if (weighted_pred_idc == 2) { + /* 8.4.3 - Derivation process for prediction weights (8-279) */ + luma_log2_weight_denom = 5; + chroma_log2_weight_denom = 5; + } } first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture; @@ -595,8 +577,8 @@ gen6_mfd_avc_slice_state(VADriverContextP ctx, OUT_BCS_BATCH(batch, (num_ref_idx_l1 << 24) | (num_ref_idx_l0 << 16) | - (slice_param->chroma_log2_weight_denom << 8) | - (slice_param->luma_log2_weight_denom << 0)); + (chroma_log2_weight_denom << 8) | + (luma_log2_weight_denom << 0)); OUT_BCS_BATCH(batch, (weighted_pred_idc << 30) | (slice_param->direct_spatial_mv_pred_flag << 29) | diff --git a/src/gen6_vme.c b/src/gen6_vme.c index a3d4354..57311dc 100644 --- a/src/gen6_vme.c +++ b/src/gen6_vme.c @@ -536,7 +536,7 @@ static void gen6_vme_pipeline_programing(VADriverContextP ctx, 0); ADVANCE_BATCH(batch); - intel_batchbuffer_end_atomic(batch); + intel_batchbuffer_end_atomic(batch); } static VAStatus gen6_vme_prepare(VADriverContextP ctx, diff --git a/src/gen6_vme.h b/src/gen6_vme.h index 6295ec2..17f199e 100644 --- a/src/gen6_vme.h +++ b/src/gen6_vme.h @@ -41,8 +41,8 @@ #define INTER_VME_OUTPUT_IN_BYTES 160 /* the first 128 bytes for MVs and the last 32 bytes for other info */ #define INTER_VME_OUTPUT_IN_DWS (INTER_VME_OUTPUT_IN_BYTES / 4) -#define MAX_INTERFACE_DESC_GEN6 MAX_GPE_KERNELS -#define MAX_MEDIA_SURFACES_GEN6 34 +#define MAX_INTERFACE_DESC_GEN6 MAX_GPE_KERNELS +#define MAX_MEDIA_SURFACES_GEN6 34 #define GEN6_VME_KERNEL_NUMBER 3 diff --git a/src/gen75_mfc.c b/src/gen75_mfc.c index 2fbac6f..c3c0e1e 100644 --- a/src/gen75_mfc.c +++ b/src/gen75_mfc.c @@ -1,5 +1,5 @@ /* - * Copyright © 2012 Intel Corporation + * Copyright © 2010-2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the @@ -91,7 +91,6 @@ gen75_mfc_pipe_mode_select(VADriverContextP ctx, { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; - assert(standard_select == MFX_FORMAT_MPEG2 || standard_select == MFX_FORMAT_AVC); @@ -220,6 +219,7 @@ gen75_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_con gen75_mfc_ind_obj_base_addr_state_bplus(ctx, encoder_context); return; } + BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); @@ -259,13 +259,13 @@ gen75_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state, BEGIN_BCS_BATCH(batch, 16); OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2)); - /*DW1. MB setting of frame */ + /*DW1. MB setting of frame */ OUT_BCS_BATCH(batch, ((width_in_mbs * height_in_mbs) & 0xFFFF)); OUT_BCS_BATCH(batch, ((height_in_mbs - 1) << 16) | ((width_in_mbs - 1) << 0)); - /* DW3 QP setting */ + /* DW3 QP setting */ OUT_BCS_BATCH(batch, (0 << 24) | /* Second Chroma QP Offset */ (0 << 16) | /* Chroma QP Offset */ @@ -2519,7 +2519,6 @@ gen75_mfc_context_destroy(void *context) dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo); mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; - for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){ dri_bo_unreference(mfc_context->reference_surfaces[i].bo); mfc_context->reference_surfaces[i].bo = NULL; diff --git a/src/gen75_mfd.c b/src/gen75_mfd.c index 0ac9d5f..0194d6f 100644 --- a/src/gen75_mfd.c +++ b/src/gen75_mfd.c @@ -23,23 +23,18 @@ * * Authors: * Xiang Haihao <haihao.xiang@intel.com> - * Zhao Yakui <yakui.zhao@intel.com> + * Zhao Yakui <yakui.zhao@intel.com> * */ +#include "sysdeps.h" -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <assert.h> #include <va/va_dec_jpeg.h> #include "intel_batchbuffer.h" #include "intel_driver.h" - #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_decoder_utils.h" - #include "gen7_mfd.h" #include "intel_media.h" @@ -276,11 +271,12 @@ gen75_mfd_pipe_buf_addr_state(VADriverContextP ctx, struct i965_driver_data *i965 = i965_driver_data(ctx); int i; - if (IS_STEPPING_BPLUS(i965)) { - gen75_mfd_pipe_buf_addr_state_bplus(ctx, decode_state, - standard_select, gen7_mfd_context); - return; - } + if (IS_STEPPING_BPLUS(i965)) { + gen75_mfd_pipe_buf_addr_state_bplus(ctx, decode_state, + standard_select, gen7_mfd_context); + return; + } + BEGIN_BCS_BATCH(batch, 25); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2)); if (gen7_mfd_context->pre_deblocking_output.valid) @@ -392,14 +388,14 @@ gen75_mfd_ind_obj_base_addr_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; - struct i965_driver_data *i965 = i965_driver_data(ctx); - if (IS_STEPPING_BPLUS(i965)) { - gen75_mfd_ind_obj_base_addr_state_bplus(ctx, slice_data_bo, - standard_select, gen7_mfd_context); - return; - } + if (IS_STEPPING_BPLUS(i965)) { + gen75_mfd_ind_obj_base_addr_state_bplus(ctx, slice_data_bo, + standard_select, gen7_mfd_context); + return; + } + BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */ @@ -454,6 +450,7 @@ gen75_mfd_bsp_buf_base_addr_state_bplus(VADriverContextP ctx, OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); + ADVANCE_BCS_BATCH(batch); } @@ -466,11 +463,11 @@ gen75_mfd_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct i965_driver_data *i965 = i965_driver_data(ctx); - if (IS_STEPPING_BPLUS(i965)) { - gen75_mfd_bsp_buf_base_addr_state_bplus(ctx, decode_state, - standard_select, gen7_mfd_context); - return; - } + if (IS_STEPPING_BPLUS(i965)) { + gen75_mfd_bsp_buf_base_addr_state_bplus(ctx, decode_state, + standard_select, gen7_mfd_context); + return; + } BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2)); @@ -481,7 +478,7 @@ gen75_mfd_bsp_buf_base_addr_state(VADriverContextP ctx, 0); else OUT_BCS_BATCH(batch, 0); - + if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, @@ -499,16 +496,6 @@ gen75_mfd_bsp_buf_base_addr_state(VADriverContextP ctx, ADVANCE_BCS_BATCH(batch); } -#if 0 -static void -gen7_mfd_aes_state(VADriverContextP ctx, - struct decode_state *decode_state, - int standard_select) -{ - /* FIXME */ -} -#endif - static void gen75_mfd_qm_state(VADriverContextP ctx, int qm_type, @@ -529,21 +516,6 @@ gen75_mfd_qm_state(VADriverContextP ctx, ADVANCE_BCS_BATCH(batch); } -#if 0 -static void -gen7_mfd_wait(VADriverContextP ctx, - struct decode_state *decode_state, - int standard_select, - struct gen7_mfd_context *gen7_mfd_context) -{ - struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; - - BEGIN_BCS_BATCH(batch, 1); - OUT_BCS_BATCH(batch, MFX_WAIT | (1 << 8)); - ADVANCE_BCS_BATCH(batch); -} -#endif - static void gen75_mfd_avc_img_state(VADriverContextP ctx, struct decode_state *decode_state, @@ -558,6 +530,8 @@ gen75_mfd_avc_img_state(VADriverContextP ctx, assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; + assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID)); + if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD) img_struct = 1; else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD) @@ -708,7 +682,8 @@ gen75_mfd_avc_directmode_state_bplus(VADriverContextP ctx, OUT_BCS_BATCH(batch, 0); } } - OUT_BCS_BATCH(batch, 0); + + OUT_BCS_BATCH(batch, 0); /* the current decoding frame/field */ va_pic = &pic_param->CurrPic; @@ -720,8 +695,8 @@ gen75_mfd_avc_directmode_state_bplus(VADriverContextP ctx, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); /* POC List */ for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { @@ -774,12 +749,12 @@ gen75_mfd_avc_directmode_state(VADriverContextP ctx, VAPictureH264 *va_pic; int i, j; - if (IS_STEPPING_BPLUS(i965)) { - gen75_mfd_avc_directmode_state_bplus(ctx, decode_state, pic_param, slice_param, - gen7_mfd_context); + if (IS_STEPPING_BPLUS(i965)) { + gen75_mfd_avc_directmode_state_bplus(ctx, decode_state, pic_param, slice_param, + gen7_mfd_context); - return; - } + return; + } BEGIN_BCS_BATCH(batch, 69); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2)); @@ -1034,7 +1009,7 @@ gen75_mfd_avc_bsd_object(VADriverContextP ctx, BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2)); OUT_BCS_BATCH(batch, - (slice_param->slice_data_size)); + (slice_param->slice_data_size - slice_param->slice_data_offset)); OUT_BCS_BATCH(batch, slice_param->slice_data_offset); OUT_BCS_BATCH(batch, (0 << 31) | @@ -2238,7 +2213,6 @@ gen75_mfd_jpeg_decode_init(VADriverContextP ctx, /* Current decoded picture */ obj_surface = decode_state->render_object; - i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('I','M','C','1'), subsampling); dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); @@ -2367,8 +2341,10 @@ gen75_mfd_jpeg_huff_table_state(VADriverContextP ctx, for (index = 0; index < num_tables; index++) { int id = va_to_gen7_jpeg_hufftable[index]; + if (!huffman_table->load_huffman_table[index]) continue; + BEGIN_BCS_BATCH(batch, 53); OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2)); OUT_BCS_BATCH(batch, id); @@ -2681,6 +2657,7 @@ gen75_jpeg_wa_pipe_buf_addr_state_bplus(VADriverContextP ctx, dri_bo_unreference(intra_bo); } + static void gen75_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) @@ -2691,10 +2668,11 @@ gen75_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx, dri_bo *intra_bo; int i; - if (IS_STEPPING_BPLUS(i965)) { - gen75_jpeg_wa_pipe_buf_addr_state_bplus(ctx, gen7_mfd_context); - return; - } + if (IS_STEPPING_BPLUS(i965)) { + gen75_jpeg_wa_pipe_buf_addr_state_bplus(ctx, gen7_mfd_context); + return; + } + intra_bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", 128 * 64, @@ -2921,7 +2899,7 @@ gen75_jpeg_wa_avc_directmode_state(VADriverContextP ctx, if (IS_STEPPING_BPLUS(i965)) { gen75_jpeg_wa_avc_directmode_state_bplus(ctx, gen7_mfd_context); return; - } + } BEGIN_BCS_BATCH(batch, 69); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2)); @@ -2948,7 +2926,7 @@ gen75_jpeg_wa_avc_directmode_state(VADriverContextP ctx, ADVANCE_BCS_BATCH(batch); } -static void +static void gen75_jpeg_wa_ind_obj_base_addr_state_bplus(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { @@ -2981,8 +2959,9 @@ gen75_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx, if (IS_STEPPING_BPLUS(i965)) { gen75_jpeg_wa_ind_obj_base_addr_state_bplus(ctx, gen7_mfd_context); - return; - } + return; + } + BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); OUT_BCS_RELOC(batch, diff --git a/src/gen75_vme.c b/src/gen75_vme.c index 2a0df88..7d13ec3 100644 --- a/src/gen75_vme.c +++ b/src/gen75_vme.c @@ -1,5 +1,5 @@ /* - * Copyright © 2012 Intel Corporation + * Copyright © 2010-2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the @@ -24,13 +24,10 @@ * Authors: * Zhao Yakui <yakui.zhao@intel.com> * Xiang Haihao <haihao.xiang@intel.com> + * */ -#include <stdio.h> -#include <stdlib.h> -#include <stdbool.h> -#include <string.h> -#include <assert.h> +#include "sysdeps.h" #include "intel_batchbuffer.h" #include "intel_driver.h" @@ -491,7 +488,6 @@ static VAStatus gen75_vme_vme_state_setup(VADriverContextP ctx, return VA_STATUS_SUCCESS; } - static void gen75_vme_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, diff --git a/src/gen75_vpp_vebox.c b/src/gen75_vpp_vebox.c index b8ca677..bf65aae 100644 --- a/src/gen75_vpp_vebox.c +++ b/src/gen75_vpp_vebox.c @@ -286,7 +286,6 @@ void hsw_veb_iecp_ace_table(VADriverContextP ctx, struct intel_vebox_context *pr void hsw_veb_iecp_tcc_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { unsigned int *p_table = (unsigned int*)(proc_ctx->iecp_state_table.ptr + 168); - // VAProcFilterParameterBuffer * tcc_param = // (VAProcFilterParameterBuffer *) proc_ctx->filter_iecp_tcc; diff --git a/src/gen75_vpp_vebox.h b/src/gen75_vpp_vebox.h index ee5a4ef..d192898 100644 --- a/src/gen75_vpp_vebox.h +++ b/src/gen75_vpp_vebox.h @@ -139,7 +139,6 @@ struct intel_vebox_context unsigned int filter_iecp_amp_num_elements; unsigned char format_convert_flags; - }; VAStatus gen75_vebox_process_picture(VADriverContextP ctx, diff --git a/src/gen7_mfd.c b/src/gen7_mfd.c index ed463d9..b89b576 100755 --- a/src/gen7_mfd.c +++ b/src/gen7_mfd.c @@ -26,15 +26,12 @@ * */ -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <assert.h> +#include "sysdeps.h" + #include <va/va_dec_jpeg.h> #include "intel_batchbuffer.h" #include "intel_driver.h" - #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_decoder_utils.h" @@ -288,16 +285,6 @@ gen7_mfd_bsp_buf_base_addr_state(VADriverContextP ctx, ADVANCE_BCS_BATCH(batch); } -#if 0 -static void -gen7_mfd_aes_state(VADriverContextP ctx, - struct decode_state *decode_state, - int standard_select) -{ - /* FIXME */ -} -#endif - static void gen7_mfd_qm_state(VADriverContextP ctx, int qm_type, @@ -318,21 +305,6 @@ gen7_mfd_qm_state(VADriverContextP ctx, ADVANCE_BCS_BATCH(batch); } -#if 0 -static void -gen7_mfd_wait(VADriverContextP ctx, - struct decode_state *decode_state, - int standard_select, - struct gen7_mfd_context *gen7_mfd_context) -{ - struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; - - BEGIN_BCS_BATCH(batch, 1); - OUT_BCS_BATCH(batch, MFX_WAIT | (1 << 8)); - ADVANCE_BCS_BATCH(batch); -} -#endif - static void gen7_mfd_avc_img_state(VADriverContextP ctx, struct decode_state *decode_state, diff --git a/src/i965_avc_bsd.c b/src/i965_avc_bsd.c index 68c6b12..80a51b8 100644 --- a/src/i965_avc_bsd.c +++ b/src/i965_avc_bsd.c @@ -25,10 +25,7 @@ * Xiang Haihao <haihao.xiang@intel.com> * */ -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <assert.h> +#include "sysdeps.h" #include "intel_batchbuffer.h" #include "intel_driver.h" diff --git a/src/i965_decoder.h b/src/i965_decoder.h index cec601d..4f7d2cc 100644 --- a/src/i965_decoder.h +++ b/src/i965_decoder.h @@ -46,7 +46,6 @@ struct gen_buffer { int valid; }; - struct hw_context * gen75_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config); diff --git a/src/i965_decoder_utils.c b/src/i965_decoder_utils.c index a45f725..4ef09b5 100644 --- a/src/i965_decoder_utils.c +++ b/src/i965_decoder_utils.c @@ -21,10 +21,10 @@ * DEALINGS IN THE SOFTWARE. */ -#include <assert.h> -#include <stddef.h> -#include <string.h> +#include "sysdeps.h" + #include <alloca.h> + #include "intel_batchbuffer.h" #include "i965_drv_video.h" #include "i965_decoder_utils.h" @@ -212,12 +212,14 @@ avc_get_first_mb_bit_offset_with_epb( { unsigned int in_slice_data_bit_offset = slice_param->slice_data_bit_offset; unsigned int out_slice_data_bit_offset; - unsigned int i, n, buf_size, data_size; + unsigned int i, j, n, buf_size, data_size, header_size; uint8_t *buf; int ret; - buf_size = slice_param->slice_data_bit_offset / 8; - data_size = slice_param->slice_data_size - slice_param->slice_data_offset; + header_size = slice_param->slice_data_bit_offset / 8; + data_size = slice_param->slice_data_size - slice_param->slice_data_offset; + buf_size = (header_size * 3 + 1) / 2; // Max possible header size (x1.5) + if (buf_size > data_size) buf_size = data_size; @@ -228,10 +230,11 @@ avc_get_first_mb_bit_offset_with_epb( ); assert(ret == 0); - for (i = 2, n = 0; i < buf_size; i++) { - if (!buf[i - 2] && !buf[i - 1] && buf[i] == 3) - i += 2, n++; + for (i = 2, j = 2, n = 0; i < buf_size && j < header_size; i++, j++) { + if (buf[i] == 0x03 && buf[i - 1] == 0x00 && buf[i - 2] == 0x00) + i += 2, j++, n++; } + out_slice_data_bit_offset = in_slice_data_bit_offset + n * 8; if (mode_flag == ENTROPY_CABAC) diff --git a/src/i965_defines.h b/src/i965_defines.h index d692433..c7163ae 100755 --- a/src/i965_defines.h +++ b/src/i965_defines.h @@ -328,15 +328,15 @@ #define MFD_JPEG_BSD_OBJECT MFX(2, 7, 1, 8) #define VEB(pipeline, op, sub_opa, sub_opb) \ - (3 << 29 | \ + (3 << 29 | \ (pipeline) << 27 | \ (op) << 24 | \ (sub_opa) << 21 | \ (sub_opb) << 16) -#define VEB_SURFACE_STATE VEB(2, 4, 0, 0) -#define VEB_STATE VEB(2, 4, 0, 2) -#define VEB_DNDI_IECP_STATE VEB(2, 4, 0, 3) +#define VEB_SURFACE_STATE VEB(2, 4, 0, 0) +#define VEB_STATE VEB(2, 4, 0, 2) +#define VEB_DNDI_IECP_STATE VEB(2, 4, 0, 3) #define I965_DEPTHFORMAT_D32_FLOAT 1 diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c index 19c298d..deee9c8 100755 --- a/src/i965_drv_video.c +++ b/src/i965_drv_video.c @@ -26,16 +26,8 @@ * Zou Nan hai <nanhai.zou@intel.com> * */ -#ifdef ANDROID -#include "config_android.h" -#else -#include "config.h" -#endif -#include <stdio.h> -#include <stdlib.h> -#include <stdbool.h> -#include <string.h> -#include <assert.h> + +#include "sysdeps.h" #ifdef HAVE_VA_X11 # include "i965_output_dri.h" @@ -2362,6 +2354,8 @@ i965_CreateImage(VADriverContextP ctx, image->component_order[1] = 'G'; image->component_order[2] = 'B'; break; + case VA_FOURCC('A','R','G','B'): + case VA_FOURCC('A','B','G','R'): case VA_FOURCC('B','G','R','A'): case VA_FOURCC('R','G','B','A'): case VA_FOURCC('B','G','R','X'): diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h index 458af2b..4314123 100644 --- a/src/i965_drv_video.h +++ b/src/i965_drv_video.h @@ -303,7 +303,6 @@ struct i965_driver_data VADisplayAttribute *display_attributes; unsigned int num_display_attributes; VADisplayAttribute *rotation_attrib; - VAContextID current_context_id; /* VA/DRI (X11) specific data */ @@ -374,7 +373,6 @@ struct i965_coded_buffer_segment #define I965_CODEDBUFFER_HEADER_SIZE ALIGN(sizeof(struct i965_coded_buffer_segment), 64) - extern VAStatus i965_MapBuffer(VADriverContextP ctx, VABufferID buf_id, /* in */ void **pbuf); /* out */ diff --git a/src/i965_output_dri.c b/src/i965_output_dri.c index 43e9300..de7be92 100644 --- a/src/i965_output_dri.c +++ b/src/i965_output_dri.c @@ -22,11 +22,10 @@ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "config.h" -#include <stdlib.h> -#include <string.h> -#include <assert.h> +#include "sysdeps.h" + #include <va/va_dricommon.h> + #include "i965_drv_video.h" #include "i965_output_dri.h" #include "dso_utils.h" @@ -119,7 +118,6 @@ i965_put_surface_dri( { struct i965_driver_data * const i965 = i965_driver_data(ctx); struct dri_vtable * const dri_vtable = &i965->dri_output->vtable; - struct dri_state * const dri_state = (struct dri_state *)ctx->drm_state; struct i965_render_state * const render_state = &i965->render_state; struct dri_drawable *dri_drawable; union dri_buffer *buffer; @@ -131,7 +129,7 @@ i965_put_surface_dri( int i, ret; /* Currently don't support DRI1 */ - if (dri_state->base.auth_type != VA_DRM_AUTH_DRI2) + if (!VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_DRI2)) return VA_STATUS_ERROR_UNKNOWN; /* Some broken sources such as H.264 conformance case FM2_SVA_C diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c index 898ed7b..2907cf7 100755 --- a/src/i965_post_processing.c +++ b/src/i965_post_processing.c @@ -215,7 +215,7 @@ static struct pp_module pp_modules_gen5[] = { { { "PL3_PL3", - PP_PL3_LOAD_SAVE_N12, + PP_PL3_LOAD_SAVE_PL3, pp_pl3_load_save_pl3_gen5, sizeof(pp_pl3_load_save_pl3_gen5), NULL, @@ -343,7 +343,6 @@ static struct pp_module pp_modules_gen5[] = { pp_plx_load_save_plx_initialize, }, - }; static const uint32_t pp_null_gen6[][4] = { @@ -458,7 +457,7 @@ static struct pp_module pp_modules_gen6[] = { { { "PL3_PL3", - PP_PL3_LOAD_SAVE_N12, + PP_PL3_LOAD_SAVE_PL3, pp_pl3_load_save_pl3_gen6, sizeof(pp_pl3_load_save_pl3_gen6), NULL, @@ -525,7 +524,7 @@ static struct pp_module pp_modules_gen6[] = { pp_plx_load_save_plx_initialize, }, - + { { "PL3_PA module", @@ -537,7 +536,7 @@ static struct pp_module pp_modules_gen6[] = { pp_plx_load_save_plx_initialize, }, - + { { "PA_NV12 module", @@ -718,7 +717,7 @@ static struct pp_module pp_modules_gen7[] = { { { "PL3_PL3", - PP_PL3_LOAD_SAVE_N12, + PP_PL3_LOAD_SAVE_PL3, pp_pl3_load_save_pl3_gen7, sizeof(pp_pl3_load_save_pl3_gen7), NULL, @@ -953,7 +952,7 @@ static struct pp_module pp_modules_gen75[] = { { { "PL3_PL3", - PP_PL3_LOAD_SAVE_N12, + PP_PL3_LOAD_SAVE_PL3, pp_pl3_load_save_pl3_gen75, sizeof(pp_pl3_load_save_pl3_gen75), NULL, @@ -1009,6 +1008,7 @@ static struct pp_module pp_modules_gen75[] = { gen7_pp_nv12_dn_initialize, }, + { { "NV12_PA module", @@ -3644,7 +3644,6 @@ gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_c sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0; sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0; sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0; - sampler_dndi[index].dw6.dn_enable = 0; sampler_dndi[index].dw6.di_enable = 1; sampler_dndi[index].dw6.di_partial = 0; @@ -3924,13 +3923,13 @@ gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_con static VAStatus ironlake_pp_initialize( - VADriverContextP ctx, + VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, - int pp_index, + int pp_index, void *filter_param ) { @@ -4055,13 +4054,13 @@ ironlake_post_processing( static VAStatus gen6_pp_initialize( - VADriverContextP ctx, + VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, - int pp_index, + int pp_index, void *filter_param ) { @@ -4157,7 +4156,7 @@ gen6_pp_initialize( va_status = VA_STATUS_ERROR_UNIMPLEMENTED; calculate_boundary_block_mask(pp_context, dst_rect); - + return va_status; } @@ -4458,14 +4457,14 @@ gen6_pp_pipeline_setup(VADriverContextP ctx, static VAStatus gen6_post_processing( - VADriverContextP ctx, + VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, - int pp_index, - void * filter_param + int pp_index, + void *filter_param ) { VAStatus va_status; @@ -4498,8 +4497,8 @@ i965_post_processing_internal( void *filter_param ) { - struct i965_driver_data *i965 = i965_driver_data(ctx); VAStatus va_status; + struct i965_driver_data *i965 = i965_driver_data(ctx); if (IS_GEN6(i965->intel.device_id) || IS_GEN7(i965->intel.device_id)) @@ -4766,10 +4765,10 @@ i965_post_processing( static VAStatus i965_image_pl1_rgbx_processing(VADriverContextP ctx, - const struct i965_surface *src_surface, - const VARectangle *src_rect, - struct i965_surface *dst_surface, - const VARectangle *dst_rect) + const struct i965_surface *src_surface, + const VARectangle *src_rect, + struct i965_surface *dst_surface, + const VARectangle *dst_rect) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_post_processing_context *pp_context = i965->pp_context; @@ -4888,12 +4887,12 @@ i965_image_pl2_processing(VADriverContextP ctx, fourcc == VA_FOURCC('R', 'G', 'B', 'X') || fourcc == VA_FOURCC('R', 'G', 'B', 'A') ) { vaStatus = i965_post_processing_internal(ctx, i965->pp_context, - src_surface, - src_rect, - dst_surface, - dst_rect, - PP_NV12_LOAD_SAVE_RGBX, - NULL); + src_surface, + src_rect, + dst_surface, + dst_rect, + PP_NV12_LOAD_SAVE_RGBX, + NULL); } else { assert(0); return VA_STATUS_ERROR_UNKNOWN; @@ -4923,8 +4922,7 @@ i965_image_pl1_processing(VADriverContextP ctx, dst_rect, PP_PA_LOAD_SAVE_NV12, NULL); - } - else if (fourcc == VA_FOURCC_YV12) { + } else if (fourcc == VA_FOURCC_YV12) { i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, @@ -4933,8 +4931,7 @@ i965_image_pl1_processing(VADriverContextP ctx, PP_PA_LOAD_SAVE_PL3, NULL); - } - else { + } else { return VA_STATUS_ERROR_UNKNOWN; } @@ -5416,3 +5413,5 @@ i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config) return (struct hw_context *)proc_context; } + + diff --git a/src/i965_post_processing.h b/src/i965_post_processing.h index b652055..4030082 100755 --- a/src/i965_post_processing.h +++ b/src/i965_post_processing.h @@ -29,7 +29,7 @@ #ifndef __I965_POST_PROCESSING_H__ #define __I965_POST_PROCESSING_H__ -#define MAX_PP_SURFACES 48 +#define MAX_PP_SURFACES 48 #define I965_PP_FLAG_TOP_FIELD 1 #define I965_PP_FLAG_BOTTOM_FIELD 2 @@ -101,6 +101,8 @@ struct pp_dn_context int dest_h; }; +struct i965_post_processing_context; + struct pp_module { struct i965_kernel kernel; diff --git a/src/i965_render.c b/src/i965_render.c index ae913a3..7fa7af7 100644 --- a/src/i965_render.c +++ b/src/i965_render.c @@ -888,6 +888,7 @@ i965_subpic_render_src_surfaces_state(VADriverContextP ctx, unsigned int index = obj_surface->subpic_render_idx; struct object_subpic *obj_subpic = obj_surface->obj_subpic[index]; struct object_image *obj_image = obj_subpic->obj_image; + assert(obj_surface); assert(obj_surface->bo); subpic_region = obj_image->bo; diff --git a/src/intel_driver.c b/src/intel_driver.c index 061d9ef..83542d9 100644 --- a/src/intel_driver.c +++ b/src/intel_driver.c @@ -27,7 +27,7 @@ * */ -#include <assert.h> +#include "sysdeps.h" #include <va/va_drmcommon.h> @@ -75,13 +75,13 @@ intel_driver_init(VADriverContextP ctx) int has_exec2, has_bsd, has_blt; assert(drm_state); - assert(drm_state->auth_type == VA_DRM_AUTH_DRI1 || - drm_state->auth_type == VA_DRM_AUTH_DRI2 || - drm_state->auth_type == VA_DRM_AUTH_CUSTOM); + assert(VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_DRI1) || + VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_DRI2) || + VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_CUSTOM)); intel->fd = drm_state->fd; - intel->dri2Enabled = (drm_state->auth_type == VA_DRM_AUTH_DRI2 || - drm_state->auth_type == VA_DRM_AUTH_CUSTOM); + intel->dri2Enabled = (VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_DRI2) || + VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_CUSTOM)); if (!intel->dri2Enabled) { return false; diff --git a/src/intel_driver.h b/src/intel_driver.h index ca6aeac..cfefa35 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -11,6 +11,7 @@ #include <intel_bufmgr.h> #include <va/va_backend.h> +#include "va_backend_compat.h" #include "intel_compiler.h" diff --git a/src/shaders/post_processing/gen5_6/Makefile.am b/src/shaders/post_processing/gen5_6/Makefile.am index 052ee53..bb8caa4 100755 --- a/src/shaders/post_processing/gen5_6/Makefile.am +++ b/src/shaders/post_processing/gen5_6/Makefile.am @@ -12,16 +12,16 @@ INTEL_PP_G4B_GEN5 = \ nv12_dn_nv12.g4b.gen5 \ nv12_dndi_nv12.g4b.gen5 \ nv12_load_save_nv12.g4b.gen5 \ + nv12_load_save_pa.g4b.gen5 \ nv12_load_save_pl3.g4b.gen5 \ + nv12_load_save_rgbx.g4b.gen5 \ nv12_scaling_nv12.g4b.gen5 \ + pa_load_save_nv12.g4b.gen5 \ + pa_load_save_pl3.g4b.gen5 \ pl3_load_save_nv12.g4b.gen5 \ + pl3_load_save_pa.g4b.gen5 \ pl3_load_save_pl3.g4b.gen5 \ - nv12_load_save_pa.g4b.gen5 \ - pl3_load_save_pa.g4b.gen5 \ - pa_load_save_nv12.g4b.gen5 \ - pa_load_save_pl3.g4b.gen5 \ - rgbx_load_save_nv12.g4b.gen5 \ - nv12_load_save_rgbx.g4b.gen5 \ + rgbx_load_save_nv12.g4b.gen5 \ $(NULL) INTEL_PP_G6B = \ @@ -29,16 +29,16 @@ INTEL_PP_G6B = \ nv12_dn_nv12.g6b \ nv12_dndi_nv12.g6b \ nv12_load_save_nv12.g6b \ + nv12_load_save_pa.g6b \ nv12_load_save_pl3.g6b \ + nv12_load_save_rgbx.g6b \ nv12_scaling_nv12.g6b \ + pa_load_save_nv12.g6b \ + pa_load_save_pl3.g6b \ pl3_load_save_nv12.g6b \ pl3_load_save_pl3.g6b \ - nv12_load_save_pa.g6b \ - pl3_load_save_pa.g6b \ - pa_load_save_nv12.g6b \ - pa_load_save_pl3.g6b \ - rgbx_load_save_nv12.g6b \ - nv12_load_save_rgbx.g6b \ + pl3_load_save_pa.g6b \ + rgbx_load_save_nv12.g6b \ $(NULL) INTEL_PP_ASM = \ @@ -46,16 +46,16 @@ INTEL_PP_ASM = \ nv12_dn_nv12.asm \ nv12_dndi_nv12.asm \ nv12_load_save_nv12.asm \ + nv12_load_save_pa.asm \ nv12_load_save_pl3.asm \ + nv12_load_save_rgbx.asm \ nv12_scaling_nv12.asm \ + pa_load_save_nv12.asm \ + pa_load_save_pl3.asm \ pl3_load_save_nv12.asm \ pl3_load_save_pl3.asm \ - nv12_load_save_pa.asm \ - pl3_load_save_pa.asm \ - pa_load_save_nv12.asm \ - pa_load_save_pl3.asm \ - rgbx_load_save_nv12.asm \ - nv12_load_save_rgbx.asm \ + pl3_load_save_pa.asm \ + rgbx_load_save_nv12.asm \ $(NULL) INTEL_PP_ASM += \ @@ -94,11 +94,11 @@ INTEL_PP_ASM += \ Common/RGB_Pack.asm \ Common/RGBX_Load_16x8.asm \ Common/RGBX_to_YUV_Coef.asm \ - Common/RGBX_Save_YUV_Fix.asm \ - Common/RGBX_Save_YUV_Float.asm \ + Common/RGBX_Save_YUV_Fix.asm \ + Common/RGBX_Save_YUV_Float.asm \ Common/YUV_to_RGBX_Coef.asm \ - Common/YUVX_Save_RGBX_Fix.asm \ - Common/YUVX_Save_RGBX_Float.asm \ + Common/YUVX_Save_RGBX_Fix.asm \ + Common/YUVX_Save_RGBX_Float.asm \ Common/SetupVPKernel.asm \ Common/readSampler16x1.asm \ Core_Kernels/AVS_SetupFirstBlock.asm \ diff --git a/src/shaders/post_processing/gen7/Makefile.am b/src/shaders/post_processing/gen7/Makefile.am index 270872a..0ecdad6 100644 --- a/src/shaders/post_processing/gen7/Makefile.am +++ b/src/shaders/post_processing/gen7/Makefile.am @@ -7,11 +7,11 @@ INTEL_PP_G7B = \ pl2_to_pa.g7b \ pl2_to_pl2.g7b \ pl2_to_pl3.g7b \ + pl2_to_rgbx.g7b \ pl3_to_pa.g7b \ pl3_to_pl2.g7b \ pl3_to_pl3.g7b \ - pl2_to_rgbx.g7b \ - rgbx_to_nv12.g7b \ + rgbx_to_nv12.g7b \ $(NULL) INTEL_PP_G4A = \ @@ -51,13 +51,12 @@ INTEL_PP_G4A = \ PL3_DN_PL3.g4a \ PL_DI_422CP.g4a \ PL_DI_PA.g4a \ + RGB_to_YUV.g4a \ Save_AVS_PA.g4a \ Save_AVS_PL3.g4a \ Save_AVS_NV12.g4a \ Save_AVS_RGB.g4a \ Save_AVS_RGBX.g4a \ - YUV_to_RGB.g4a \ - RGB_to_YUV.g4a \ Set_AVS_Buf_0123_BGRA.g4a \ Set_AVS_Buf_0123_PL2.g4a \ Set_AVS_Buf_0123_PL3.g4a \ @@ -65,6 +64,7 @@ INTEL_PP_G4A = \ Set_AVS_Buf_0123_VYUA.g4a \ Set_Layer_0.g4a \ VP_Setup.g4a \ + YUV_to_RGB.g4a \ $(NULL) INTEL_PP_ASM = $(INTEL_PP_G7B:%.g7b=%.asm) diff --git a/src/shaders/vme/inter_frame_haswell.asm b/src/shaders/vme/inter_frame_haswell.asm index 63934ac..6305c3c 100644 --- a/src/shaders/vme/inter_frame_haswell.asm +++ b/src/shaders/vme/inter_frame_haswell.asm @@ -371,6 +371,7 @@ __mb_hwdep_end: asr (2) mb_ref_win.0<1>:w mb_mvp_ref.0<2,2,1>:w 2:w {align1}; add (2) mb_ref_win.8<1>:w mb_ref_win.0<2,2,1>:w 3:w {align1}; and (2) mb_ref_win.16<1>:uw mb_ref_win.8<2,2,1>:uw 0xFFFC:uw {align1}; + /* m2, get the MV/Mb cost passed from constant buffer when spawning thread by MEDIA_OBJECT */ mov (8) vme_m2<1>:UD r1.0<8,8,1>:UD {align1}; @@ -396,7 +397,6 @@ mov (1) vme_msg_5.20<1>:UW CHROMA_ROW.6<0,1,0>:UW {align1}; /* m6 */ - mov (4) vme_msg_6.16<1>:UD CHROMA_ROW.8<4,4,1>:UD {align1}; mov (8) vme_msg_6.0<1>:UW CHROMA_COL.2<16,8,2>:UW {align1}; @@ -674,7 +674,6 @@ __EXIT: mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; - nop ; nop ; /* Compare three word data to get the min value */ @@ -716,4 +715,3 @@ cmp_a_ge_b: (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; cmp_end: RETURN {align1}; - diff --git a/src/shaders/vme/intra_frame_haswell.asm b/src/shaders/vme/intra_frame_haswell.asm index 022a3e6..54c0de5 100644 --- a/src/shaders/vme/intra_frame_haswell.asm +++ b/src/shaders/vme/intra_frame_haswell.asm @@ -116,7 +116,6 @@ and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1}; /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; - /* Disable DC HAAR component when calculating HARR SATD block */ mov (1) tmp_reg0.0<1>:UW DC_HARR_DISABLE:UW {align1}; mov (1) vme_m1.30<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; diff --git a/src/sysdeps.h b/src/sysdeps.h new file mode 100644 index 0000000..71bfb4d --- /dev/null +++ b/src/sysdeps.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2012 Intel Corporation. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SYSDEPS_H +#define SYSDEPS_H + +#ifdef ANDROID + +# include "config_android.h" + +#else + +#ifdef HAVE_CONFIG_H +# include "config.h" +#endif + +#endif /* ANDROID */ + +#include <stdio.h> +#include <stdlib.h> +#include <stdbool.h> +#include <string.h> +#include <stdint.h> +#include <assert.h> + +#endif /* SYSDEPS_H */ diff --git a/src/va_backend_compat.h b/src/va_backend_compat.h new file mode 100644 index 0000000..f5c9f75 --- /dev/null +++ b/src/va_backend_compat.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2012 Intel Corporation. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VA_BACKEND_COMPAT_H +#define VA_BACKEND_COMPAT_H + +#include <va/va_backend.h> + +#if VA_CHECK_VERSION(0,33,0) +# include <va/va_drmcommon.h> + +# define VA_CHECK_DRM_AUTH_TYPE(ctx, type) \ + (((struct drm_state *)(ctx)->drm_state)->auth_type == (type)) + +#else +# include <va/va_dricommon.h> + +# define VA_CHECK_DRM_AUTH_TYPE(ctx, type) \ + (((struct dri_state *)(ctx)->dri_state)->driConnectedFlag == (type)) + +# define drm_state dri_state +# define VA_DRM_AUTH_DRI1 VA_DRI1 +# define VA_DRM_AUTH_DRI2 VA_DRI2 +# define VA_DRM_AUTH_CUSTOM VA_DUMMY +#endif + +#endif /* VA_BACKEND_COMPAT_H */ |