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authorZhao Yakui <yakui.zhao@intel.com>2013-12-23 15:59:22 +0800
committerYakui Zhao <yakui.zhao@intel.com>2013-12-23 15:59:22 +0800
commit428c4cd38901059a7c145db95f9ffb83419da8a1 (patch)
treec00074bd2115baa22f17111aa2754e8e79ba3e75 /src/i965_post_processing.c
parent037b37bb5ba68e5628f4381b024ffac105408ddc (diff)
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Configure VPP parameter for RGBX input so that Haswell/Ivy uses the same gen7_pp_plx_avs_initialize
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Diffstat (limited to 'src/i965_post_processing.c')
-rwxr-xr-xsrc/i965_post_processing.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c
index c523f57..377df39 100755
--- a/src/i965_post_processing.c
+++ b/src/i965_post_processing.c
@@ -936,7 +936,7 @@ static struct pp_module pp_modules_gen7[] = {
NULL,
},
- gen7_pp_rgbx_avs_initialize,
+ gen7_pp_plx_avs_initialize,
},
{
@@ -1202,7 +1202,7 @@ static struct pp_module pp_modules_gen75[] = {
NULL,
},
- gen7_pp_rgbx_avs_initialize,
+ gen7_pp_plx_avs_initialize,
},
{
@@ -3572,6 +3572,16 @@ gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_con
pp_static_parameter->grf2.avs_wa_enable = 1; /* must be set for GEN7 */
if (IS_HASWELL(i965->intel.device_id))
pp_static_parameter->grf2.avs_wa_enable = 0; /* HSW don't use the WA */
+
+ if (pp_static_parameter->grf2.avs_wa_enable) {
+ int src_fourcc = pp_get_surface_fourcc(ctx, src_surface);
+ if ((src_fourcc == VA_FOURCC('R', 'G', 'B', 'A')) ||
+ (src_fourcc == VA_FOURCC('R', 'G', 'B', 'X')) ||
+ (src_fourcc == VA_FOURCC('B', 'G', 'R', 'A')) ||
+ (src_fourcc == VA_FOURCC('B', 'G', 'R', 'X'))) {
+ pp_static_parameter->grf2.avs_wa_enable = 0;
+ }
+ }
pp_static_parameter->grf2.avs_wa_width = dw;
pp_static_parameter->grf2.avs_wa_one_div_256_width = (float) 1.0 / (256 * dw);