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| author | Zhao Yakui <yakui.zhao@intel.com> | 2013-04-16 13:57:51 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2013-12-19 10:24:37 +0800 |
| commit | 0c5e3ab5bff002c4abef40621907452d879c2ef7 (patch) | |
| tree | 2b7024a35ea52dae08f2605eacf4ae32cb6699a4 /src/i965_post_processing.c | |
| parent | 79987a38fce53979675c09ba5b339d1179d45680 (diff) | |
| download | libva-intel-driver-0c5e3ab5bff002c4abef40621907452d879c2ef7.tar.gz libva-intel-driver-0c5e3ab5bff002c4abef40621907452d879c2ef7.tar.bz2 libva-intel-driver-0c5e3ab5bff002c4abef40621907452d879c2ef7.zip | |
Use the horizontal/vertical alignment for VPP surface on BDW
This is hardware requirement.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Diffstat (limited to 'src/i965_post_processing.c')
| -rwxr-xr-x | src/i965_post_processing.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c index 6108a84..48743c4 100755 --- a/src/i965_post_processing.c +++ b/src/i965_post_processing.c @@ -2080,6 +2080,11 @@ gen8_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_cont ss->ss2.width = width - 1; ss->ss2.height = height - 1; ss->ss3.pitch = pitch - 1; + + /* Always set 1(align 4 mode) per B-spec */ + ss->ss0.vertical_alignment = 1; + ss->ss0.horizontal_alignment = 1; + gen8_pp_set_surface_tiling(ss, tiling); gen8_render_set_surface_scs(ss); dri_bo_emit_reloc(ss_bo, |