Merge branch 'master' into staging

Conflicts:
	NEWS
	configure.ac
	src/Makefile.am
	src/gen6_mfc.c
	src/gen6_mfd.c
	src/gen6_vme.c
	src/gen6_vme.h
	src/gen75_mfc.c
	src/gen75_mfd.c
	src/gen75_vme.c
	src/gen75_vpp_vebox.c
	src/gen75_vpp_vebox.h
	src/gen7_mfd.c
	src/i965_avc_bsd.c
	src/i965_decoder.h
	src/i965_decoder_utils.c
	src/i965_defines.h
	src/i965_drv_video.c
	src/i965_drv_video.h
	src/i965_encoder.c
	src/i965_encoder.h
	src/i965_output_dri.c
	src/i965_post_processing.c
	src/i965_post_processing.h
	src/i965_render.c
	src/i965_structs.h
	src/intel_driver.c
	src/object_heap.c
	src/shaders/post_processing/Common/AYUV_Load_16x8.asm
	src/shaders/post_processing/Common/AYUV_Load_16x8.inc
	src/shaders/post_processing/Common/Init_All_Regs.asm
	src/shaders/post_processing/Makefile.am
	src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm
	src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc
	src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm
	src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm
	src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm
	src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc
	src/shaders/post_processing/gen5_6/Makefile.am
	src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5
	src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b
	src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5
	src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b
	src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
	src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
	src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5
	src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b
	src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5
	src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b
	src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5
	src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b
	src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5
	src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b
	src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5
	src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b
	src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5
	src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b
	src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5
	src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b
	src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5
	src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b
	src/shaders/post_processing/gen7/EOT.g4a
	src/shaders/post_processing/gen7/Makefile.am
	src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a
	src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a
	src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a
	src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a
	src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a
	src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a
	src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a
	src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a
	src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a
	src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a
	src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a
	src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a
	src/shaders/post_processing/gen7/Save_AVS_NV12.g4a
	src/shaders/post_processing/gen7/Save_AVS_PA.g4a
	src/shaders/post_processing/gen7/Save_AVS_PL3.g4a
	src/shaders/post_processing/gen7/Save_AVS_RGB.g4a
	src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a
	src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a
	src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a
	src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a
	src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a
	src/shaders/post_processing/gen7/Set_Layer_0.g4a
	src/shaders/post_processing/gen7/VP_Setup.g4a
	src/shaders/vme/Makefile.am
	src/shaders/vme/inter_frame_haswell.asm
	src/shaders/vme/inter_frame_haswell.g75b
	src/shaders/vme/intra_frame_haswell.asm
	src/shaders/vme/intra_frame_haswell.g75b
	src/shaders/vme/vme75.inc
	src/shaders/vme/vme7_mpeg2.inc

1 files changed, 4 insertions, 5 deletions

diff --git a/src/gen75_mfc.c b/src/gen75_mfc.c
index 2fbac6f..c3c0e1e 100644
--- a/src/gen75_mfc.c
+++ b/src/gen75_mfc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright © 2012 Intel Corporation
+ * Copyright © 2010-2012 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the
@@ -91,7 +91,6 @@ gen75_mfc_pipe_mode_select(VADriverContextP ctx,
 {
     struct intel_batchbuffer *batch = encoder_context->base.batch;
     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
     assert(standard_select == MFX_FORMAT_MPEG2 ||
            standard_select == MFX_FORMAT_AVC);
 
@@ -220,6 +219,7 @@ gen75_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_con
 	gen75_mfc_ind_obj_base_addr_state_bplus(ctx, encoder_context);
 	return;
     }
+
     BEGIN_BCS_BATCH(batch, 11);
 
     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
@@ -259,13 +259,13 @@ gen75_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state,
     BEGIN_BCS_BATCH(batch, 16);
 
     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
-	/*DW1. MB setting of frame */
+    /*DW1. MB setting of frame */
     OUT_BCS_BATCH(batch,
                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
     OUT_BCS_BATCH(batch, 
                   ((height_in_mbs - 1) << 16) | 
                   ((width_in_mbs - 1) << 0));
-	/* DW3 QP setting */
+    /* DW3 QP setting */
     OUT_BCS_BATCH(batch, 
                   (0 << 24) |	/* Second Chroma QP Offset */
                   (0 << 16) |	/* Chroma QP Offset */
@@ -2519,7 +2519,6 @@ gen75_mfc_context_destroy(void *context)
     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
 
-
     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
         dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
         mfc_context->reference_surfaces[i].bo = NULL;