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| author | Zhao Yakui <yakui.zhao@intel.com> | 2013-12-23 15:59:22 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2014-02-27 10:26:25 +0800 |
| commit | 8071b71638e068ac5f0e4a9aca1f87dcf79fcba1 (patch) | |
| tree | f9b82747ed8ef5f6bf44f13bb5bcfd96b4885a5c | |
| parent | 88018fcb61d54e6f25a35a580f2c1e5c7147b354 (diff) | |
| download | libva-intel-driver-8071b71638e068ac5f0e4a9aca1f87dcf79fcba1.tar.gz libva-intel-driver-8071b71638e068ac5f0e4a9aca1f87dcf79fcba1.tar.bz2 libva-intel-driver-8071b71638e068ac5f0e4a9aca1f87dcf79fcba1.zip | |
Configure VPP parameter for RGBX input so that Haswell/Ivy uses the same gen7_pp_plx_avs_initialize
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
| -rwxr-xr-x | src/i965_post_processing.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c index ddafba4..4661c28 100755 --- a/src/i965_post_processing.c +++ b/src/i965_post_processing.c @@ -894,7 +894,7 @@ static struct pp_module pp_modules_gen7[] = { NULL, }, - gen7_pp_rgbx_avs_initialize, + gen7_pp_plx_avs_initialize, }, { @@ -1145,7 +1145,7 @@ static struct pp_module pp_modules_gen75[] = { NULL, }, - gen7_pp_rgbx_avs_initialize, + gen7_pp_plx_avs_initialize, }, { @@ -3490,6 +3490,16 @@ gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_con pp_static_parameter->grf2.avs_wa_enable = 1; /* must be set for GEN7 */ if (IS_HASWELL(i965->intel.device_id)) pp_static_parameter->grf2.avs_wa_enable = 0; /* HSW don't use the WA */ + + if (pp_static_parameter->grf2.avs_wa_enable) { + int src_fourcc = pp_get_surface_fourcc(ctx, src_surface); + if ((src_fourcc == VA_FOURCC('R', 'G', 'B', 'A')) || + (src_fourcc == VA_FOURCC('R', 'G', 'B', 'X')) || + (src_fourcc == VA_FOURCC('B', 'G', 'R', 'A')) || + (src_fourcc == VA_FOURCC('B', 'G', 'R', 'X'))) { + pp_static_parameter->grf2.avs_wa_enable = 0; + } + } pp_static_parameter->grf2.avs_wa_width = dw; pp_static_parameter->grf2.avs_wa_one_div_256_width = (float) 1.0 / (256 * dw); |