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| author | Gwenole Beauchesne <gwenole.beauchesne@intel.com> | 2014-05-14 13:33:07 +0200 |
|---|---|---|
| committer | Gwenole Beauchesne <gwenole.beauchesne@intel.com> | 2014-06-02 19:30:43 +0200 |
| commit | 18d0aee33fd4a32f846475cf31a2be6499b17b4b (patch) | |
| tree | cdfe715b7d24a79c8908cc77f85b8bca040c0232 | |
| parent | 3afe0514162332e923092000940ee8e99979a817 (diff) | |
| download | libva-intel-driver-18d0aee33fd4a32f846475cf31a2be6499b17b4b.tar.gz libva-intel-driver-18d0aee33fd4a32f846475cf31a2be6499b17b4b.tar.bz2 libva-intel-driver-18d0aee33fd4a32f846475cf31a2be6499b17b4b.zip | |
surface: fix geometry (size, layout) of grayscale surfaces.
Fix size of the allocated buffer used to represent grayscale (Y800)
surfaces. Only the luminance component is needed, thus implying a
single plane.
Likewise, update render routines to only submit the first plane.
The existing render kernels readily only care about that single
plane.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
| -rw-r--r-- | src/gen8_render.c | 3 | ||||
| -rwxr-xr-x | src/i965_drv_video.c | 9 | ||||
| -rw-r--r-- | src/i965_render.c | 3 |
3 files changed, 11 insertions, 4 deletions
diff --git a/src/gen8_render.c b/src/gen8_render.c index ca731d2..074fec4 100644 --- a/src/gen8_render.c +++ b/src/gen8_render.c @@ -276,6 +276,9 @@ gen8_render_src_surfaces_state( gen8_render_src_surface_state(ctx, 1, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); /* Y */ gen8_render_src_surface_state(ctx, 2, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); + if (obj_surface->fourcc == VA_FOURCC_Y800) /* single plane for grayscale */ + return; + if (obj_surface->fourcc == VA_FOURCC_NV12) { gen8_render_src_surface_state(ctx, 3, region, region_pitch * obj_surface->y_cb_offset, diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c index bf15208..7a0320b 100755 --- a/src/i965_drv_video.c +++ b/src/i965_drv_video.c @@ -861,6 +861,7 @@ bpp_1stplane_by_fourcc(unsigned int fourcc) case VA_FOURCC_YUY2: return 2; + case VA_FOURCC_Y800: case VA_FOURCC_YV12: case VA_FOURCC_IMC3: case VA_FOURCC_IYUV: @@ -2868,13 +2869,13 @@ i965_check_alloc_surface_bo(VADriverContextP ctx, case VA_FOURCC_Y800: assert(subsampling == SUBSAMPLE_YUV400); - obj_surface->cb_cr_pitch = obj_surface->width; + obj_surface->cb_cr_pitch = 0; obj_surface->cb_cr_width = 0; obj_surface->cb_cr_height = 0; - obj_surface->y_cb_offset = obj_surface->height; - obj_surface->y_cr_offset = obj_surface->y_cb_offset + ALIGN(obj_surface->cb_cr_height, 32); + obj_surface->y_cb_offset = 0; + obj_surface->y_cr_offset = 0; region_width = obj_surface->width; - region_height = obj_surface->height + ALIGN(obj_surface->cb_cr_height, 32) * 2; + region_height = obj_surface->height; break; diff --git a/src/i965_render.c b/src/i965_render.c index aed78c0..9d0e846 100644 --- a/src/i965_render.c +++ b/src/i965_render.c @@ -876,6 +876,9 @@ i965_render_src_surfaces_state( i965_render_src_surface_state(ctx, 1, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); /* Y */ i965_render_src_surface_state(ctx, 2, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); + if (obj_surface->fourcc == VA_FOURCC_Y800) /* single plane for grayscale */ + return; + if (obj_surface->fourcc == VA_FOURCC_NV12) { i965_render_src_surface_state(ctx, 3, region, region_pitch * obj_surface->y_cb_offset, |